IEICE SEARCH SYSTEM

Masato INAGI

A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks Masatoshi NAKAMURA Masato INAGI Kazuya TANIGAWA Tetsuo HIRONAKA Masayuki SATO Takashi ISHIGURO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 324-334 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: reconfigurable device, physical design, placement, routing, MPLD, FPGA, EDA,
	Summary \| Full Text:PDF (1.7MB)

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3539-3547 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: FPGA prototyping, ILP, I/O pins constraint, verification, time-multiplexed I/O,
	Summary \| Full Text:PDF (308.3KB)

A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/05/01 Vol. E90-A No. 5 pp. 924-931 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: circuit partitioning, time-multiplexed I/O, FPGA, pin constraint,
	Summary \| Full Text:PDF (402.5KB)

An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm Kengo R. AZEGAMI Masato INAGI Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/03/01 Vol. E85-A No. 3 pp. 655-663 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: circuit partition, hyper-graph partition, network flow, min-cut, integrated circuit design,
	Summary \| Full Text:PDF (616.4KB)