Masashi TAWADA


Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams
Ryota ISHIKAWA Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2018/07/01
Vol. E101-A  No. 7  pp. 1002-1013
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
stochastic computingstochastic numberduplicatorbit re-arrangementre-convergence path
 Summary | Full Text:PDF(1.5MB)

A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories
Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2018/07/01
Vol. E101-A  No. 7  pp. 1045-1052
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
non-volatile memorybit-write-reducingerror-correcting codesclustering conditionsS-bit flip conditionsS-bound graphcluster graphrelaxed REC code
 Summary | Full Text:PDF(378.1KB)

A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories
Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2398-2411
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
non-volatile memorybit-write-reducingerror-correcting codesclustering conditionsS-bit flip conditionsS-bound graphcluster graphREC code
 Summary | Full Text:PDF(1.6MB)

Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories
Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2484-2493
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
non-volatile memorymaximum-writing bitserror-correcting codesDoughnut codecode expansion
 Summary | Full Text:PDF(1.6MB)

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory
Masashi TAWADA Shinji KIMURA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2494-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
non-volatile memorybit-write reductionenergy reductionwrite-reduction codeerror-correcting code
 Summary | Full Text:PDF(1.5MB)

A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches
Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6  pp. 1283-1292
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
cache simulationoptimaize cache memorymulticore cache
 Summary | Full Text:PDF(1.4MB)