Masao TAGUCHI

Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface
Yoshinori OKAJIMA  Masao TAGUCHI  Miki YANAGAWA  Koichi NISHIMURA  Osamu HAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/20
Vol. E79-C  No. 6  pp. 798-807
Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
DLL,  synchronous interface,  DRAM,  bus timing skew, 
  Summary |  Full Text:PDF (726.8KB)
High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application
Masao TAGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/20
Vol. E77-C  No. 12  pp. 1944-1950
Type of Manuscript: INVITED PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processor Interfaces
Keyword: 
I/O,  interface,  termination,  CTT, 
  Summary |  Full Text:PDF (529.7KB)
Minority Carrier Collection in 256 M-bit DRAM Cell on Incidence of Alpha-Particle Analyzed by Three-Dimensional Device Simulation
Sumiko OSHIDA  Masao TAGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/20
Vol. E76-C  No. 11  pp. 1604-1610
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
soft error,  device simulation,  256 M-bit DRAM, 
  Summary |  Full Text:PDF (529.2KB)