Masanori HASHIMOTO


Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
Koichi MITSUNARI Jaehoon YU Takao ONOYE Masanori HASHIMOTO 
Publication:   
Publication Date: 2018/09/01
Vol. E101-A  No. 9  pp. 1298-1307
Type of Manuscript:  Special Section PAPER (Special Section on Intelligent Transport Systems)
Category: 
Keyword: 
decision tree ensembletask schedulingobject detectionmachine learningembedded systems
 Summary | Full Text:PDF(2.6MB)

Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors
Yutaka MASUDA Takao ONOYE Masanori HASHIMOTO 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1452-1463
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
electrical timing errorsoftware-based error detectionEDM transformationerror detection
 Summary | Full Text:PDF(2.3MB)

Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator
Shoichi IIZUKA Yuma HIGUCHI Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2607-2613
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
variation sensorRing Oscillatordevice-parameter estimationperformance adaptation
 Summary | Full Text:PDF(1.3MB)

Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification
Daisuke FUKUDA Kenichi WATANABE Yuji KANAZAWA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1467-1474
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
etchingmanufacturabilitymodeling variability
 Summary | Full Text:PDF(1.5MB)

A Process and Temperature Tolerant Oscillator-Based True Random Number Generator
Takehiko AMAKI Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2393-2399
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
true random number generatorhardware random number generatoroscillator-based random number generator
 Summary | Full Text:PDF(1.5MB)

Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm
Daisuke FUKUDA Kenichi WATANABE Naoki IDANI Yuji KANAZAWA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2373-2382
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
Edge-over-ErosionCMPmanufacturabilitymachine learning
 Summary | Full Text:PDF(1.9MB)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing
Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Hajime SHIMADA Kazutoshi KOBAYASHI Hiroyuki KANBARA Hiroyuki OCHI Takashi IMAGAWA Kazutoshi WAKABAYASHI Masanori HASHIMOTO Takao ONOYE Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2518-2529
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
reconfigurable architecturesoft errorradiation testbehavioral synthesisstate machine
 Summary | Full Text:PDF(3.8MB)

Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices
Hiroaki KONOURA Takashi IMAGAWA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/07/01
Vol. E97-A  No. 7  pp. 1468-1482
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
fault avoidancelifetime enhancementmean-time-to-failure (MTTF)partial reconfiguration
 Summary | Full Text:PDF(5.6MB)

NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time
Hiroaki KONOURA Toshihiro KAMEDA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/07/01
Vol. E97-A  No. 7  pp. 1483-1491
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
NBTINBTI mitigationperformance degradationscan pathagingreliability
 Summary | Full Text:PDF(2.5MB)

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects
Ryo HARADA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/07/01
Vol. E97-A  No. 7  pp. 1461-1467
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
soft errorsingle event transient (SET)pulse-widthpulse-width modulationmeasurement circuitwithin-die process variation
 Summary | Full Text:PDF(1.8MB)

Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices
Toshihiro KAMEDA Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1624-1631
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Test and Verification
Keyword: 
field testfault avoidancecoarse-grained reconfigurable device
 Summary | Full Text:PDF(1.5MB)

Jitter Amplifier for Oscillator-Based True Random Number Generator
Takehiko AMAKI Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/03/01
Vol. E96-A  No. 3  pp. 684-696
Type of Manuscript:  PAPER
Category: Cryptography and Information Security
Keyword: 
true random number generatorjitter
 Summary | Full Text:PDF(2.2MB)

Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling
Igors HOMJAKOVS Masanori HASHIMOTO Tetsuya HIROSE Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/02/01
Vol. E96-A  No. 2  pp. 459-468
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
signal-dependent samplingMINIMAXpeak-detection
 Summary | Full Text:PDF(2MB)

A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning
Shuta KIMURA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2292-2300
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
post-silicon tuningbody bias clusteringprocess variationbody biasingstatistical static timing analysis
 Summary | Full Text:PDF(1.1MB)

Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis
Takashi ENAMI Takashi SATO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2261-2271
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
power distribution networkdecoupling capacitancetiming analysisstatistical static timing analysisdecap insertionwire sizing
 Summary | Full Text:PDF(1.4MB)

Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure
Yasumichi TAKAI Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2220-2225
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
power gatingon-chip power supply noiserush currentwell structure
 Summary | Full Text:PDF(1.9MB)

Extracting Device-Parameter Variations with RO-Based Sensors
Ken-ichi SHINKAI Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2537-2544
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
variation sensormanufacturing variabilitydevice-parameterring oscillator
 Summary | Full Text:PDF(1016.2KB)

Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
Hiroaki KONOURA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2545-2553
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
NBTIstress probabilitytiming analysis
 Summary | Full Text:PDF(1.4MB)

Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise
Takaaki OKUMURA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/10/01
Vol. E94-A  No. 10  pp. 1948-1953
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
power supply noiseFlip-Flopsetup timehold timetiming analysis
 Summary | Full Text:PDF(826.8KB)

Gate Delay Estimation in STA under Dynamic Power Supply Noise
Takaaki OKUMURA Fumihiro MINAMI Kenji SHIMAZAKI Kimihiko KUWADA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2447-2455
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
power supply noisegate delaytiming analysis
 Summary | Full Text:PDF(1.3MB)

Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation
Takashi ENAMI Shinyu NINOMIYA Ken-ichi SHINKAI Shinya ABE Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2399-2408
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
statistical timing analysisclock jittersetup verificationstructural correlationpower supply noise
 Summary | Full Text:PDF(964.2KB)

Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation
Shinyu NINOMIYA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2441-2446
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
statistical timing analysismanufacturing variability
 Summary | Full Text:PDF(1.1MB)

Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution
Ryo HARADA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2417-2423
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
soft errorsingle event transient (SET)pulse widthmeasurement circuit
 Summary | Full Text:PDF(675KB)

Prediction of Self-Heating in Short Intra-Block Wires
Ken-ichi SHINKAI Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/03/01
Vol. E93-A  No. 3  pp. 583-594
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
self-heatingtemperatureinterconnectlocal wireprocess scaling
 Summary | Full Text:PDF(1.8MB)

Impact of Self-Heating in Wire Interconnection on Timing
Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 388-392
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
interconnectdelay variationparasitic resistancethermaltemperatureself-heatSoC
 Summary | Full Text:PDF(221.9KB)

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3016-3023
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
low powerleakagegate delay modelvariation
 Summary | Full Text:PDF(1.1MB)

Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
Hiroshi FUKETA Masanori HASHIMOTO Yukio MITSUYAMA Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3094-3102
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
adaptive speed controlsubthreshold circuittiming error predictiontiming margin variability
 Summary | Full Text:PDF(612.3KB)

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 990-997
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
SSTAoutputtransition timegate delay modelprocess variation
 Summary | Full Text:PDF(2.6MB)

An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
Koichi HAMAMOTO Hiroshi FUKETA Masanori HASHIMOTO Yukio MITSUYAMA Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/02/01
Vol. E92-C  No. 2  pp. 281-285
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
body biaslayout
 Summary | Full Text:PDF(335.2KB)

Impact of Well Edge Proximity Effect on Timing
Toshiki KANAMOTO Yasuhiro OGASAHARA Keiko NATSUME Kenji YAMAGUCHI Hiroyuki AMISHIRO Tetsuya WATANABE Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3461-3464
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
well edge proximity effectWPEdelaytiming
 Summary | Full Text:PDF(377.8KB)

Area-Efficient Reconfigurable Architecture for Media Processing
Yukio MITSUYAMA Kazuma TAKAHASHI Rintaro IMAI Masanori HASHIMOTO Takao ONOYE Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3651-3662
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
reconfigurablemedia processingmulti-standardarea-efficiencydynamic reconfiguration
 Summary | Full Text:PDF(901.6KB)

Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
Shinya ABE Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3481-3487
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
mesh-style clock distributionclock skew
 Summary | Full Text:PDF(500.8KB)

Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration
Masanori HASHIMOTO Jangsombatsiri SIRIPORN Akira TSUCHIYA Haikun ZHU Chung-Kuan CHENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3474-3480
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
eye-diagramon-chip transmission linewaveform distortionresistive terminationshunt conductance
 Summary | Full Text:PDF(801.1KB)

Timing Analysis Considering Temporal Supply Voltage Fluctuation
Masanori HASHIMOTO Junji YAMAGUCHI Takashi SATO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 655-660
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Verification and Timing Analysis
Keyword: 
timing analysisdynamic power supply noise
 Summary | Full Text:PDF(450.7KB)

Timing Analysis Considering Spatial Power/Ground Level Variation
Masanori HASHIMOTO Junji YAMAGUCHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2661-2668
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
timing analysispower supply noisegate delay modelpower/ground level variation
 Summary | Full Text:PDF(497.6KB)

Transistor Sizing of LCD Driver Circuit for Technology Migration
Masanori HASHIMOTO Takahito IJICHI Shingo TAKAHASHI Shuji TSUKIYAMA Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2712-2717
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
technology migrationtransistor sizingLCD driver circuit
 Summary | Full Text:PDF(311.1KB)

Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling
Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/06/01
Vol. E90-C  No. 6  pp. 1267-1273
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
on-chip transmission-linetermination
 Summary | Full Text:PDF(855.9KB)

Proposal of Metrics for SSTA Accuracy Evaluation
Hiroyuki KOBAYASHI Nobuto ONO Takashi SATO Jiro IWAI Hidenari NAKASHIMA Takaaki OKUMURA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4  pp. 808-814
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
statistical static timing analysisstatistical max operationDFMSoC
 Summary | Full Text:PDF(1.1MB)

Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect
Yasuhiro OGASAHARA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4  pp. 724-731
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
signal integrityinterconnect delaycapacitive crosstalkinductive crosstalk
 Summary | Full Text:PDF(553.8KB)

Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3666-3670
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
interconnectdelay variationparasitic capacitanceSoC
 Summary | Full Text:PDF(433.5KB)

A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays
Shingo TAKAHASHI Shuji TSUKIYAMA Masanori HASHIMOTO Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3538-3545
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
active matrix LCDCAD toolcolumn driversampling pulsesampling switch
 Summary | Full Text:PDF(399.2KB)

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
Toshiki KANAMOTO Tatsuhiko IKEDA Akira TSUCHIYA Hidetoshi ONODERA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3560-3568
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
substrateinterconnectresistanceinductanceSoC
 Summary | Full Text:PDF(1.4MB)

On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature
Takashi SATO Junji ICHIMIYA Nobuto ONO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3491-3499
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
thermal gradient simulationleakage powertemperature-dependent leakage powerpower calculationleakage model
 Summary | Full Text:PDF(1MB)

Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line
Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3585-3593
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
parameter extractiontransmission-linefrequency dependence
 Summary | Full Text:PDF(450.9KB)

On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
Takashi SATO Junji ICHIMIYA Nobuto ONO Koutaro HACHIYA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3382-3389
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Prediction and Analysis
Keyword: 
thermal simulationthermal gradienttemperature flatteningclock skewreliabilitytiming
 Summary | Full Text:PDF(959.9KB)

Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance
Atsushi KUROKAWA Masanori HASHIMOTO Akira KASEBE Zhangcai HUANG Yun YANG Yasuaki INOUE Ryosuke INAGAKI Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3453-3462
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
capacitance formulacapacitance calculationcapacitance extractioninterconnect capacitance
 Summary | Full Text:PDF(1.1MB)

Successive Pad Assignment for Minimizing Supply Voltage Drop
Takashi SATO Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3429-3436
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Power/Ground Network
Keyword: 
successive pad assignment (SPA)incremental matrix inversion (IMI)voltage droppower distribution network
 Summary | Full Text:PDF(557.9KB)

Effects of On-Chip Inductance on Power Distribution Grid
Atsushi MURAMATSU Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3564-3572
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
power distribution networkon-chip inductancepower supply noisedecoupling capacitance
 Summary | Full Text:PDF(789.2KB)

Statistical Analysis of Clock Skew Variation in H-Tree Structure
Masanori HASHIMOTO Tomonori YAMAMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3375-3381
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Prediction and Analysis
Keyword: 
clock skewmanufacturing variabilityenvironmental variabilitytransition time constraintstatistical analysisclock distribution
 Summary | Full Text:PDF(826.7KB)

Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling
Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 885-891
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
global interconnecthigh-speed signalingperformance limitation
 Summary | Full Text:PDF(1MB)

A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL
Takahito MIYAZAKI Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/03/01
Vol. E88-C  No. 3  pp. 437-444
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock generation PLLLC oscillatorring oscillatorperformance predictionjitterpower consumptionchip area
 Summary | Full Text:PDF(401.8KB)

Crosstalk Noise Optimization by Post-Layout Transistor Sizing
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3251-3257
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
crosstalk noisecapacitive coupling noisetransistor sizinggate sizingpost-layout optimization
 Summary | Full Text:PDF(300.4KB)

Crosstalk Noise Estimation for Generic RC Trees
Masanori HASHIMOTO Masao TAKAHASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2965-2973
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
crosstalk noisecapacitive couplingnoise estimationsignal integrity
 Summary | Full Text:PDF(854.2KB)

Experimental Study on Cell-Base High-Performance Datapath Design
Masanori HASHIMOTO Yoshiteru HAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3204-3207
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
datapath designbit-slice layouttransistor sizingcell-base design
 Summary | Full Text:PDF(227.8KB)

Representative Frequency for Interconnect R(f)L(f)C Extraction
Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2942-2951
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
interconnectextractionfrequency-dependent
 Summary | Full Text:PDF(788KB)

Increase in Delay Uncertainty by Performance Optimization
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2799-2802
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Analysis
Keyword: 
performance optimizationdelay increasestatistical timing analysisdelay uncertaintytransistor sizing
 Summary | Full Text:PDF(297.5KB)

Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2769-2777
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
transistor sizinglow power designcell-base designpost-layout optimizationgate sizing
 Summary | Full Text:PDF(806.1KB)

A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2558-2568
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Optimization
Keyword: 
statistical static timing analysisstatic timing analysisgate resizingtransistor sizingperformance optimization
 Summary | Full Text:PDF(418.4KB)

A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
Masanori HASHIMOTO Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/01/25
Vol. E82-A  No. 1  pp. 159-166
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
input reorderingtransistor reorderingpower estimation
 Summary | Full Text:PDF(317.8KB)