Masanori HARIYAMA


Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators
Yasuhiro TAKEI Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2658-2669
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
heterogeneous multicoreFPGAcustom acceleratorsreconfigurable architecture
 Summary | Full Text:PDF(2.3MB)

Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators
Yasuhiro TAKEI Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2576-2586
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
heterogeneous multicore processorFPGAMultimedia processingHigh-performance-computing
 Summary | Full Text:PDF(2.4MB)

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1632-1644
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
FPGAreconfigurable LSIself-timed circuitasynchronous circuit
 Summary | Full Text:PDF(3.8MB)

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation
Yoshitaka HIRAMATSU Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Toru NOJIRI Kunio UCHIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/12/01
Vol. E95-C  No. 12  pp. 1872-1882
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
block matchingheterogeneous multi-coredynamically reconfigurable processordata transferaccelerator
 Summary | Full Text:PDF(4.4MB)

Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates
Zhengfan XIA Shota ISHIHARA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/08/01
Vol. E95-C  No. 8  pp. 1434-1443
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
asynchronous pipelinedual-railcritical datapath
 Summary | Full Text:PDF(2.1MB)

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors
Hasitha Muthumala WAIDYASOORIYA Yosuke OHBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 354-363
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
memory allocationpartitioningreconfigurable processors
 Summary | Full Text:PDF(844.7KB)

Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Shota ISHIHARA Ryoto TSUCHIYA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/10/01
Vol. E94-C  No. 10  pp. 1669-1679
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
mixed synchronous/asynchronous designreconfigurable VLSIfour-phase dual-rail encodingself-timed architectureGALS (Globally Asynchronous Locally Synchronous)
 Summary | Full Text:PDF(3.4MB)

Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions
Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/01/01
Vol. E94-A  No. 1  pp. 342-351
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
memory allocationparallel data accessaddressing
 Summary | Full Text:PDF(2MB)

Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation
Hasitha Muthumala WAIDYASOORIYA Daisuke OKUMURA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2570-2580
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
heterogeneous multi-core processortask-allocationsystem-on-chip
 Summary | Full Text:PDF(1.3MB)

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
Shota ISHIHARA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8  pp. 1338-1348
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
reconfigurable VLSIfield-programmable VLSILEDR (Level-Encoded Dual-Rail) encoding4-phase dual-rail encodingself-timed architecture
 Summary | Full Text:PDF(1.6MB)

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals
Shota ISHIHARA Noriaki IDOBATA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2134-2144
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Application of Multiple-Valued VLSI
Keyword: 
dynamically programmable gate arraymulti-context switchlogic-in-memory circuitmultiple-valued threshold logicnonvolatile storagenon-destructive operation
 Summary | Full Text:PDF(2.1MB)

Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 539-549
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
DPGAmulti-contextasynchronous FPGA
 Summary | Full Text:PDF(1.8MB)

Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages
Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3596-3606
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesislow powerinterconnection networkgenetic algorithm
 Summary | Full Text:PDF(1.2MB)

Memory Allocation for Multi-Resolution Image Processing
Yasuhiro KOBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10  pp. 2386-2397
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
high-level synthesisinterconnection-aware architecturestereo vision
 Summary | Full Text:PDF(645KB)

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Masanori HARIYAMA Shota ISHIHARA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1419-1426
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
FPGAsreconfigurable VLSIsasynchronous architectureLEDR (Level-Encoded Dual-Rail) encoding
 Summary | Full Text:PDF(668.6KB)

Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling
Masanori HARIYAMA Naoto YOKOYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 479-486
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
stereo visionschedulingallocation
 Summary | Full Text:PDF(1021.6KB)

Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment
Hasitha Muthumala WAIDYASOORIYA Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 517-525
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
dynamically-programmable gate arraymulti-context FPGAconfiguration data redundancy
 Summary | Full Text:PDF(1.5MB)

A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates
Masanori HARIYAMA Sho OGATA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1655-1661
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
time-multiplexed FPGAdynamically reconfigurable architectureDPGAbit-serial architecture
 Summary | Full Text:PDF(866.4KB)

Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification
Masanori HARIYAMA Shigeo YAMADERA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1551-1558
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
automatic synthesisschedulingmodule selectiondata-path designoptimization
 Summary | Full Text:PDF(1.2MB)

Low-Power Field-Programmable VLSI Using Multiple Supply Voltages
Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3298-3305
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword: 
reconfigurable processorFPGAmultiple-supply-voltage scheme
 Summary | Full Text:PDF(923.3KB)

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture
Masanori HARIYAMA Yasuhiro KOBAYASHI Haruka SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3516-3522
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
stereo visionFPGAschedulingallocation
 Summary | Full Text:PDF(812.1KB)

Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access
Masanori HARIYAMA Haruka SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1486-1491
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
stereo visionSAD (sum of absolute differences)memory allocationlogic-in-memory architecture
 Summary | Full Text:PDF(1.1MB)

Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture
Masanori HARIYAMA Weisheng CHONG Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1897-1902
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
reconfigurable architectureFPGAbit-serial architecture
 Summary | Full Text:PDF(530.8KB)

Highly-Parallel Stereo Vision VLSI Processor Based on an Optimal Parallel Memory Access Scheme
Masanori HARIYAMA Seunghwan LEE Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3  pp. 382-389
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
motion stereomemory allocationfunctional-unit allocation
 Summary | Full Text:PDF(2.5MB)

An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access
Seunghwan LEE Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/12/25
Vol. E83-D  No. 12  pp. 2122-2130
Type of Manuscript:  PAPER
Category: Image Processing, Image Pattern Recognition
Keyword: 
motion stereoFPGA-based processormemory allocationfunctional unit allocation
 Summary | Full Text:PDF(1.9MB)

Collision Detection VLSI Processor for Intelligent Vehicles Using a Hierarchically-Content-Addressable Memory
Masanori HARIYAMA Kazuhiro SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1722-1729
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Processors
Keyword: 
hierarchical collision detectionarea-time product minimizationCAMpath planning
 Summary | Full Text:PDF(1.4MB)

A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme
Seunghwan LEE Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/11/25
Vol. E80-C  No. 11  pp. 1491-1498
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
3-D instrumentationepipolar constraintblock matching algorithmspecial-purpose VLSI processormemory interleaving
 Summary | Full Text:PDF(644.6KB)

Design of a CAM-Based Collision Detection VLSI Processor for Robotics
Masanori HARIYAMA Michitaka KANEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7  pp. 1108-1115
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
special-purpose VLSIcontent-addressable memory (CAM)rectangular solid representationCORDIC algorithms
 Summary | Full Text:PDF(649.1KB)

A Collision Detection Processor for Intelligent Vehicles
Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Vol. E76-C  No. 12  pp. 1804-1811
Type of Manuscript:  Special Section PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
special-purpose VLSIcontent-addressable memoryrectangular solid representation
 Summary | Full Text:PDF(650.5KB)