Masanao YAMAOKA


Adaptive Circuits for the 0.5-V Nanoscale CMOS Era
Kiyoo ITOH Masanao YAMAOKA Takashi OSHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 216-233
Type of Manuscript:  INVITED PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
minimum operating voltageSRAMDRAMFD-SOIFinFET
 Summary | Full Text:PDF(2.2MB)

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones
Makoto ISHIKAWA Tatsuya KAMEI Yuki KONDO Masanao YAMAOKA Yasuhisa SHIMAZAKI Motokazu OZAWA Saneaki TAMAKI Mikio FURUYAMA Tadashi HOSHI Fumio ARAKAWA Osamu NISHII Kenji HIROSE Shinichi YOSHIOKA Toshihiro HATTORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 528-535
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
application processorcellular phonepipeline structureresume-standbylow powerlow leakage
 Summary | Full Text:PDF(1.3MB)

Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
Kazutoshi KOBAYASHI Masanao YAMAOKA Yukifumi KOBAYASHI Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2400-2408
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
VLSIfunctional memoryDRAMparallel processorblock matching
 Summary | Full Text:PDF(868.6KB)