Masakazu TANAKA


Impact of Self-Heating in Wire Interconnection on Timing
Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 388-392
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
interconnectdelay variationparasitic resistancethermaltemperatureself-heatSoC
 Summary | Full Text:PDF(221.9KB)

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3016-3023
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
low powerleakagegate delay modelvariation
 Summary | Full Text:PDF(1.1MB)

Capacity Improvement of Multihop Inter-Vehicle Communication Networks by STBC Cooperative Relaying
Toshiaki KOIKE Masakazu TANAKA Susumu YOSHIDA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2005/09/01
Vol. E88-B  No. 9  pp. 3546-3553
Type of Manuscript:  Special Section PAPER (Special Section on Advances in Ad Hoc Mobile Communications and Networking)
Category: 
Keyword: 
ITSmultihopinter-vehicle communicationsSTBCcooperative relayingcapacity
 Summary | Full Text:PDF(377.3KB)

An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays
Shuji TSUKIYAMA Masakazu TANAKA Masahiro FUKUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2746-2754
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Analysis
Keyword: 
static timing analysisstatistical approachcorrelationnormal distributionCMOS combinatorial circuits
 Summary | Full Text:PDF(473.5KB)

Design Optimization by Using Flexible Pipelined Modules
Masahiro FUKUI Masakazu TANAKA Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2521-2528
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
Keyword: 
pipelinedesign tuningmodule generation
 Summary | Full Text:PDF(648.9KB)

An Automatic Layout Generator for Bipolar Analog Modules
Takao ONOYE Akihisa YAMADA Itthichai ARUNGSRISANGCHAI Masakazu TANAKA Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1306-1314
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
layout generatoranalog curcuitone-dimensianal arrayblock compaction
 Summary | Full Text:PDF(708.3KB)