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Masakazu AOKI

Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis Masakazu AOKI Shin-ichi OHKAWA Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 647-654 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: modeling transistor variations, within-die variation, statistical analysis for transistor parameters, SRAM cell sensitivity analysis, process window for SRAM cell operation,
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Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an LSI Chip Masakazu AOKI Shin-ichi OHKAWA Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/05/01 Vol. E88-C No. 5 pp. 788-795 Type of Manuscript: Special Section PAPER (Special Section on Microelectronic Test Structures) Category: Keyword: within-die parameter variation, random variation, systematic variation, correlation length, fitting function,
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Half-V_cc Plate Nonvolatile DRAMs with Ferroelectric Capacitors Kan TAKEUCHI Katsumi MATSUNO Yoshinobu NAKAGOME Masakazu AOKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/02/20 Vol. E79-C No. 2 pp. 234-242 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: ferroelectric memory, DRAM, half-V _cc plate, nonvolatile memory,
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Dynamic Terminations for Low-Power High-Speed Chip Interconnection in Portable Equipment Takayuki KAWAHARA Masakazu AOKI Katsutaka KIMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/20 Vol. E78-C No. 4 pp. 404-413 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: Digital Circuits Keyword: dynamic termination, transmission line, low-power, high-speed,
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Low-Voltage and Low-Power ULSI Circuit Techniques Masakazu AOKI Kiyoo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/20 Vol. E77-C No. 8 pp. 1351-1360 Type of Manuscript: INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: General Technology Keyword: battery operation, subthreshold current, switched power-line scheme, self-reverse biasing, switched source impedance, hierarchical power line, partial activation of circuit blocks, charge recycle, reference-voltage generator,
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Sub-1-µA Dynamic Reference Voltage Generator for Battery-Operated DRAM's Hitoshi TANAKA Yoshinobu NAKAGOME Jun ETOH Eiji YAMASAKI Masakazu AOKI Kazuyuki MIYAZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/05/20 Vol. E77-C No. 5 pp. 778-783 Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) Category: Keyword:
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The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips Takao WATANABE Masakazu AOKI Katsutaka KIMURA Takeshi SAKATA Kiyoo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/20 Vol. E76-C No. 7 pp. 1206-1214 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Neural Networks and Chips Keyword: DRAM-based neuro-chip, 10⁶-synapse neural network, 1.5-V digital chip, 0.5-µm CMOS design rule,
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Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's Yoshinobu NAKAGOME Kiyoo ITOH Masanori ISODA Kan TAKEUCHI Masakazu AOKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/05/20 Vol. E76-C No. 5 pp. 754-759 Type of Manuscript: Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993)) Category: Keyword:
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Stabilization of Voltage Limiter Circuit for High-Density DRAM's Using Pole-Zero Compensation Hitoshi TANAKA Masakazu AOKI Jun ETOH Masashi HORIGUCHI Kiyoo ITOH Kazuhiko KAJIGAYA Tetsurou MATSUMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/11/20 Vol. E75-C No. 11 pp. 1333-1343 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Keyword: memory, DRAM, voltage limiter, pole-zero compensation,
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