Masahiro IIDA


Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core
Motoki AMAGASAKI Yuki NISHITANI Kazuki INOUE Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI 
Publication:   
Publication Date: 2017/04/01
Vol. E100-D  No. 4  pp. 633-644
Type of Manuscript:  INVITED PAPER (Special Section on Award-winning Papers)
Category: 
Keyword: 
fault tolerantfault recoveryFPGA-IP
 Summary | Full Text:PDF(2.6MB)

SLM: A Scalable Logic Module Architecture with Less Configuration Memory
Motoki AMAGASAKI Ryo ARAKI Masahiro IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2500-2506
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAscalable logic moduletechnology mapping
 Summary | Full Text:PDF(736.9KB)

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC
Motoki AMAGASAKI Qian ZHAO Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2  pp. 252-261
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
fault tolerantFPGAIP-core
 Summary | Full Text:PDF(3MB)

FPGA Design Framework Combined with Commercial VLSI CAD
Qian ZHAO Kazuki INOUE Motoki AMAGASAKI Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1602-1612
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
FPGACADrouting
 Summary | Full Text:PDF(1.2MB)

Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration
Yoshihiro ICHINOMIYA Tsuyoshi KIMURA Motoki AMAGASAKI Morihiro KUGA Masahiro IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2347-2356
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
FPGApartial reconfigurationfault-injection analysissoft-errordependability
 Summary | Full Text:PDF(1MB)

An Easily Testable Routing Architecture and Prototype Chip
Kazuki INOUE Masahiro KOGA Motoki AMAGASAKI Masahiro IIDA Yoshinobu ICHIDA Mitsuro SAJI Jun IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 303-313
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
design for testabilityhomogeneous architecturetest methodprototype chip
 Summary | Full Text:PDF(3.3MB)

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization
Masahiro IIDA Motoki AMAGASAKI Yasuhiro OKAMOTO Qian ZHAO Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 294-302
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
reconfigurable logicCOGRENPN-equivalent classes
 Summary | Full Text:PDF(596.3KB)

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
Masahiro IIDA Masahiro KOGA Kazuki INOUE Motoki AMAGASAKI Yoshinobu ICHIDA Mitsuro SAJI Jun IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 548-556
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
reconfigurable logicFeRAMpower-gatingnon-volatile flip-flopNV-FFVGLC
 Summary | Full Text:PDF(5.2MB)

A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices
Hiroshi SHINOHARA Hideaki MONJI Masahiro IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12  pp. 1986-1989
Type of Manuscript:  Special Section LETTER (Special Section on Reconfigurable Systems)
Category: 
Keyword: 
low power techniqueresource sharingdynamically reconfigurable logic
 Summary | Full Text:PDF(743.8KB)

Time-Memory Trade-off Cryptanalysis for Limited Key on FPGA-Based Parallel Machine RASH
Katsumi TAKAHASHI Hiroai ASAMI Katsuto NAKAJIMA Masahiro IIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5  pp. 781-788
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
RASHFPGAreconfigurable computingtime-memory trade-off cryptanalysis
 Summary | Full Text:PDF(596.6KB)

Configurable and Reconfigurable Computing for Digital Signal Processing
Toshinori SUEYOSHI Masahiro IIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/03/01
Vol. E85-A  No. 3  pp. 591-599
Type of Manuscript:  INVITED PAPER (Special Section on the Trend of Digital Signal Processing and Its Future Direction)
Category: LSI/Signal Processors
Keyword: 
configurable computingreconfigurable computingdigital signal processingFPGA
 Summary | Full Text:PDF(1.1MB)