Masahiro GOSHIMA


Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology
Junji YAMADA Ushio JIMBO Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 232-244
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
register fileregister cachedigital designfreePDK
 Summary | Full Text:PDF(3.2MB)

Applying Razor Flip-Flops to SRAM Read Circuits
Ushio JIMBO Junji YAMADA Ryota SHIOYA Masahiro GOSHIMA 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 245-258
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
random variationtiming fault detection and recoverydynamic voltage and frequency scaling (DVFS)SRAM
 Summary | Full Text:PDF(2MB)

An Inductive Method to Select Simulation Points
MinSeong CHOI Takashi FUKUDA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 2891-2900
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
simulation pointsampling simulationmicroarchitectureprocessor architecturesimulationcomputer architecture
 Summary | Full Text:PDF(2.6MB)

FXA: Executing Instructions in Front-End for Energy Efficiency
Ryota SHIOYA Ryo TAKAMI Masahiro GOSHIMA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/04/01
Vol. E99-D  No. 4  pp. 1092-1107
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processorhybrid in-order/out-of-order coreenergy efficiency
 Summary | Full Text:PDF(1.3MB)

Address Order Violation Detection with Parallel Counting Bloom Filters
Naruki KURATA Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 580-593
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
processor architectureload-store queuebloom filterlow-energy technologies
 Summary | Full Text:PDF(1.8MB)

Register Indirect Jump Target Forwarding
Ryota SHIOYA Naruki KURATA Takashi TOYOSHIMA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/02/01
Vol. E96-D  No. 2  pp. 278-288
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architectureregister indirect jumpobject-oriented programming
 Summary | Full Text:PDF(1.7MB)

Low-Overhead Architecture for Security Tag
Ryota SHIOYA Daewung KIM Kazuo HORIO Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1  pp. 69-78
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architecturetagged architectureinformation securityinformation flow tracking
 Summary | Full Text:PDF(507.1KB)

Ultra Dependable Processor
Shuichi SAKAI Masahiro GOSHIMA Hidetsugu IRIE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1386-1393
Type of Manuscript:  INVITED PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
microprocessor architecturedependable computingattacksfaultserrorsfailuressoft errorstiming errorstamper resistanceinformation flowinjection attackdependability manager
 Summary | Full Text:PDF(1.1MB)

ReVolver/C40: A Scalable Parallel Computer for Volume Rendering--Design and Implementation--
Shin-ichiro MORI Tomoaki TSUMURA Masahiro GOSHIMA Yasuhiko NAKASHIMA Hiroshi NAKASHIMA Shinji TOMITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10  pp. 2006-2015
Type of Manuscript:  Special Section PAPER (Special Issue on Development of Advanced Computer Systems)
Category: 
Keyword: 
volume renderingparallel processingscalable architecturevisualization
 Summary | Full Text:PDF(675.2KB)

A Large-Scale IP and Lambda Integrated Router Architecture
Michihiro AOKI Miki HIRANO Nobuaki MATSUURA Takashi KURIMOTO Takashi MIYAMURA Masahiro GOSHIMA Keisuke KABASHIMA Shigeo URUSHIDANI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/08/01
Vol. E86-B  No. 8  pp. 2302-2309
Type of Manuscript:  Special Section PAPER (Special Issue on Photonic IP Network Technologies for Next Generation Broadband Access)
Category: 
Keyword: 
scalable switch architecturelambda routerIP routerarrayed waveguide grating
 Summary | Full Text:PDF(1.5MB)