Masahiko TOYONAGA


An Efficient and Reliable Watermarking System for IP Protection
Tingyuan NIE Masahiko TOYONAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/09/01
Vol. E90-A  No. 9  pp. 1932-1939
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
intellectual property protection (IPP)post layout designincremental router
 Summary | Full Text:PDF(1.1MB)

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling
Keiichi KUROKAWA Takuya YASUI Yoichi MATSUMURA Masahiko TOYONAGA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2746-2755
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Clock Scheduling
Keyword: 
clock schedulingclock tree synthesishigh-speedlow power
 Summary | Full Text:PDF(1.4MB)

A Practical Clock Tree Synthesis for Semi-Synchronous Circuits
Keiichi KUROKAWA Takuya YASUI Masahiko TOYONAGA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2705-2713
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout
Keyword: 
semi-synchronous circuitclock schedulingenvironmental and manufacturing conditionszero skew clock treevarious timing clock tree
 Summary | Full Text:PDF(1007KB)

WSSA: A High Performance Simulated Annealing and Its Application to Transistor Placement
Shunji SAIKA Masahiro FUKUI Masahiko TOYONAGA Toshiro AKINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2584-2591
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Synthesis
Keyword: 
simulated annealingtemperature schedulingphase transitionplacement optimizationcell synthesis
 Summary | Full Text:PDF(665.9KB)

A Multi-Layer Channel Router Using Simulated Annealing
Masahiko TOYONAGA Chie IWASAKI Yoshiaki SAWADA Toshiro AKINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2085-2091
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
channel routersimulated annealinglayer assignmentcompaction
 Summary | Full Text:PDF(648.3KB)

A New Approach of Fractal-Analysis Based Module Clustering for VLSI Placement
Masahiko TOYONAGA Shih-Tsung YANG Isao SHIRAKAWA Toshiro AKINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2045-2052
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
clusteringfractal analysisplacementpartitioning
 Summary | Full Text:PDF(747.9KB)

Placement Optimization by Trembling Spot-Check
Masahiko TOYONAGA Hiroaki OKUDE Toshiro AKINO 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/12/25
Vol. E72-E  No. 12  pp. 1350-1359
Type of Manuscript:  Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology
Keyword: 
 Summary | Full Text:PDF(813.8KB)