IEICE SEARCH SYSTEM

Masahide MIYAZAKI

A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips Masahide MIYAZAKI Tomokazu YONEDA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/04/01 Vol. E89-D No. 4 pp. 1490-1497 Type of Manuscript: PAPER Category: Dependable Computing Keyword: SoC, test scheduling, wrapper, design for test, memory BIST,
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A DFT Selection Method for Reducing Test Application Time of System-on-Chips Masahide MIYAZAKI Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 609-619 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: SoC Testing Keyword: test scheduling, test access mechanism, wrapper, design for test,
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A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint Toshinori HOSOKAWA Hiroshi DATE Masahide MIYAZAKI Michiaki MURAOKA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-D No. 12 pp. 2674-2683 Type of Manuscript: Special Section PAPER (Special Issue on Dependable Computing) Category: Test Keyword: test plan grouping, test controllers, partly compacted test plan tables, RTL data paths, hierarchical test generation,
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