Masaharu IMAI


Deformable Part Model Based Arrhythmia Detection Using Time Domain Features
Yuuka HIRAO Yoshinori TAKEUCHI Masaharu IMAI Jaehoon YU 
Publication:   
Publication Date: 2017/11/01
Vol. E100-A  No. 11  pp. 2221-2229
Type of Manuscript:  Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Digital Signal Processing
Keyword: 
arrhythmia detectionelectrocardiogramdeformable part modeltime domain features
 Summary | Full Text:PDF(1.5MB)

A New Available Bandwidth Estimation Method Using RTT for a Bottleneck Link
Masaharu IMAI Yoshio SUGIZAKI Koichi ASATANI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2014/04/01
Vol. E97-B  No. 4  pp. 712-720
Type of Manuscript:  PAPER
Category: Network
Keyword: 
RTTactive measurementavailable bandwidthbottleneck link
 Summary | Full Text:PDF(2.3MB)

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring
Hirofumi IWATO Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 487-494
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
pressure sensingurinary bladderSoClow powerASIP
 Summary | Full Text:PDF(1.3MB)

Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design
Ittetsu TANIGUCHI Ayataka KOBAYASHI Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2659-2668
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
forward error correction (FEC)decoder model
 Summary | Full Text:PDF(1019.6KB)

Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor
Takuji HIEDA Hiroaki TANAKA Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3258-3267
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
partial forwardinginstruction schedulingcompilerdesign space exploration
 Summary | Full Text:PDF(561.2KB)

Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems
Hassan A. YOUNESS Keishi SAKANUSHI Yoshinori TAKEUCHI Ashraf SALEM Abdel-Moneim WAHDAN Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 1088-1095
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
optimal schedulingtask graphsstate-space searchA*geometric analysis
 Summary | Full Text:PDF(1.4MB)

Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors
Ittetsu TANIGUCHI Praveen RAGHAVAN Murali JAYAPALA Francky CATTHOOR Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 1161-1173
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
address generation unit (AGU)reconfigurable architectureASIP designarchitecture exploration
 Summary | Full Text:PDF(1.1MB)

Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling
Yuki KOBAYASHI Murali JAYAPALA Praveen RAGHAVAN Francky CATTHOOR Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2  pp. 604-612
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
compilers for low energyVLIW processorsloop buffers
 Summary | Full Text:PDF(626.2KB)

Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram
Hiroaki TANAKA Yoshinori TAKEUCHI Keishi SAKANUSHI Masaharu IMAI Hiroki TAGAWA Yutaka OTA Nobu MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2800-2809
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
compilerSIMD instructionsmulti-valued decision diagram
 Summary | Full Text:PDF(555.8KB)

FOREWORD
Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2913-2913
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(58.3KB)

A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors
Shinsuke KOBAYASHI Kentaro MITA Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2586-2595
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Hardware/Software Codesign
Keyword: 
compiler generationASIPdesign space exploration
 Summary | Full Text:PDF(527.6KB)

Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation
Shinsuke KOBAYASHI Yoshinori TAKEUCHI Akira KITAJIMA Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3  pp. 748-754
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
multi-threadingvery long instruction word (VLIW)instruction level parallelismthread level parallelismHW/SW co-design
 Summary | Full Text:PDF(577.8KB)

VLSI Architecture for Real-Time Fractal Image Coding Processors
Hideki YAMAUCHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/03/25
Vol. E83-A  No. 3  pp. 452-458
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
VLSI architectureimage codingfractal compression
 Summary | Full Text:PDF(1MB)

Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description
Makiko ITOH Yoshinori TAKEUCHI Masaharu IMAI Akichika SHIOMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/03/25
Vol. E83-A  No. 3  pp. 394-400
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
pipelined processormicro-operation descriptionHDL generationinstruction set processor
 Summary | Full Text:PDF(624.1KB)

A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency
Katsuya SHINOHARA Norimasa OHTSUKI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2356-2365
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
performance optimizationclock frequency tuningpipelined ASIPsHW/SW co-design
 Summary | Full Text:PDF(729.6KB)

Performance Evaluation of STRON: A Hardware Implementation of a Real-Time OS
Takumi NAKANO Yoshiki KOMATSUDAIRA Akichika SHIOMI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2375-2382
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
real-time systemreal-time OShardware OSsilicon TRON (STRON)silicon OS (SOS)
 Summary | Full Text:PDF(794.4KB)

Effectiveness of a High Speed Context Switching Method Using Register Bank
Jun-ichi ITO Takumi NAKANO Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2661-2667
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: LSI Architecture
Keyword: 
hard real-time system real-time OS context switching register bankcontext switching module (CSM)hardware OS
 Summary | Full Text:PDF(623.2KB)

An Optimization Algorithm for High Performance ASIP Design with Considering the RAM and ROM Sizes
Nguyen Ngoc BINH Masaharu IMAI Yoshinori TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2612-2620
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Co-design
Keyword: 
ASIPHW/SW partitioningperformance estimationRAMROM
 Summary | Full Text:PDF(766.2KB)

Design Optimization by Using Flexible Pipelined Modules
Masahiro FUKUI Masakazu TANAKA Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2521-2528
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
Keyword: 
pipelinedesign tuningmodule generation
 Summary | Full Text:PDF(648.9KB)

FOREWORD
Masaharu IMAI Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2475-2475
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(140.8KB)

Optimal Instruction Set Design through Adaptive Detabase Generation
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 347-353
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
ASIP, HW/SW partioningperformance estimationadaptive database generation
 Summary | Full Text:PDF(568.6KB)

An Instruction Set Optimization Algorithm for Pipelined ASIPs
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1707-1714
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ASIPpipelined architectureHW/SW partitioningperformance estimationPEAS-I system
 Summary | Full Text:PDF(679.5KB)

An Efficient Scheduling Algorithm for Pipelined Instruction Set Processor and Its Application to ASIP Hardware/Software Codesign
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI Yoshimichi HONMA Jun SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3  pp. 353-362
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
schedulingpipeline hazardsHW/SW partitioningASIPperformance estimationPEAS-I system
 Summary | Full Text:PDF(914.9KB)

PEAS-I: A Hardware/Software Codesign System for ASIP Development
Jun SATO Alauddin Y. ALOMARY Yoshimichi HONMA Takeharu NAKATA Akichika SHIOMI Nobuyuki HIKICHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3  pp. 483-491
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Category: Computer Aided Design (CAD)
Keyword: 
ASIPhardware/software codesignPEAS-ICPU core design automationapplication program development tool generation
 Summary | Full Text:PDF(818.7KB)

An ASIP Instruction Set Optimization Algorithm with Functional Module Sharing Constraint
Alauddin Y. ALOMARY Masaharu IMAI Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1713-1720
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ASIPinstruction set optimizationbranch-and-bound methodfunctional module sharingPEAS system
 Summary | Full Text:PDF(648.9KB)

An Integer Programming Approach to Instruction Set Selection Problem
Alauddin Y. ALOMARY Masaharu IMAI Jun SATO Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1849-1857
Type of Manuscript:  PAPER
Category: VLSI Design Technology
Keyword: 
ASIPVLSI CADinstruction set optimizationbranch-and-bound method
 Summary | Full Text:PDF(745.3KB)

New Trend and Future Issues of Hardware Description Language and High-Level Synthesis
Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3  pp. 307-313
Type of Manuscript:  INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
HDLhigh-level synthesisVHDLverilog HDLUDL/IPARTHENONSFL
 Summary | Full Text:PDF(501.8KB)

Proposal of a New Design Environment for Application Specific Integrated Processor: IDEAS
Jun SATO Masaharu IMAI Tetsuya HAKATA Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/05/25
Vol. E74-A  No. 5  pp. 1014-1016
Type of Manuscript:  Special Section LETTER (Special Issue on 1991 Spring Natl. Conv. IEICE)
Category: VLSI Design
Keyword: 
 Summary | Full Text:PDF(213KB)

The Architecture of a Flexible Servo Motor Control Processor--FSP-3--
Jun SATO Tsutomu KIMURA Masaharu IMAI Frank de SCHEPPER Kazuo YAMAZAKI Masashi NAGASE Shin-ichiro YAMAMOTO 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/04/25
Vol. E73-E  No. 4  pp. 513-515
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Spring National Convention IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF(245.9KB)

A Double-Tree Structured Multicomputer System and Its Application to Combinatorial Problems
Masaharu IMAI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1986/09/25
Vol. E69-E  No. 9  pp. 1002-1010
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
 Summary | Full Text:PDF(661.4KB)

Memory Space Controllable Search Strategies for Branch-and-Bound Algorithms
Masaharu IMAI Yuuji YOSHIDA Teruo FUKUMURA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1982/05/25
Vol. E65-E  No. 5  pp. 257-264
Type of Manuscript:  PAPER
Category: Miscellaneous
Keyword: 
 Summary | Full Text:PDF(482.7KB)