Manabu KOBAYASHI


Probabilistic Fault Diagnosis and its Analysis in Multicomputer Systems
Manabu KOBAYASHI Toshiyasu MATSUSHIMA Shigeichi HIRASAWA 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12  pp. 2072-2081
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding theory and techniques
Keyword: 
multicomputer systemssystem-level fault diagnosisprobabilistic fault diagnosisintermittent faultsdensity evolution
 Summary | Full Text:PDF(999.7KB)

Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs
Manabu KOBAYASHI Hiroshi NINOMIYA Yasuyuki MIURA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/05/01
Vol. E97-A  No. 5  pp. 1051-1058
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
reconfigurable logic circuitambipolar double-gate devicesdynamic logicCNTFETs
 Summary | Full Text:PDF(817.2KB)

Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs
Hiroshi NINOMIYA Manabu KOBAYASHI Yasuyuki MIURA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2  pp. 675-678
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
reconfigurable logic circuit designambipolar devicedouble-gate CNTFETbinary decision diagramarithmetic logic unit
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Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs
Manabu KOBAYASHI Hiroshi NINOMIYA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7  pp. 1642-1644
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
reconfigurable logic circuitambipolar double-gate devicesdynamic logicCNTFETs
 Summary | Full Text:PDF(244.8KB)

Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram
Hiroshi NINOMIYA Manabu KOBAYASHI Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/01/01
Vol. E96-A  No. 1  pp. 356-359
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
reconfigurable logic designambipolar devicedouble gate CNTFETbinary decision diagram
 Summary | Full Text:PDF(615.3KB)

Adaptive Decoding Algorithms for Low-Density Parity-Check Codes over the Binary Erasure Channel
Gou HOSOYA Hideki YAGI Manabu KOBAYASHI Shigeichi HIRASAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/10/01
Vol. E92-A  No. 10  pp. 2418-2430
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
low-density parity-check codebelief-propagation decodingbinary erasure channelstopping set
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Density Evolution Analysis of Robustness for LDPC Codes over the Gilbert-Elliott Channel
Manabu KOBAYASHI Hideki YAGI Toshiyasu MATSUSHIMA Shigeichi HIRASAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/10/01
Vol. E91-A  No. 10  pp. 2754-2764
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
LDPC codesdensity evolutionGilbert-Elliott channelrobustness
 Summary | Full Text:PDF(391.7KB)

An Improved Method of Reliability-Based Maximum Likelihood Decoding Algorithms Using an Order Relation among Binary Vectors
Hideki YAGI Manabu KOBAYASHI Toshiyasu MATSUSHIMA Shigeichi HIRASAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/10/01
Vol. E87-A  No. 10  pp. 2493-2502
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
maximum likelihood decodingsoft decision decodingreliability measurelinear block codesorder relation
 Summary | Full Text:PDF(262.2KB)

Complexity Reduction of the Gazelle and Snyders Decoding Algorithm for Maximum Likelihood Decoding
Hideki YAGI Manabu KOBAYASHI Shigeichi HIRASAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/10/01
Vol. E86-A  No. 10  pp. 2461-2472
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
maximum likelihood decodinginformation set decodingmost reliable basisreliability measurelinear block codes
 Summary | Full Text:PDF(342.4KB)

An Efficient Heuristic Search Method for Maximum Likelihood Decoding of Linear Block Codes Using Dual Codes
Tomotsugu OKADA Manabu KOBAYASHI Shigeichi HIRASAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Vol. E85-A  No. 2  pp. 485-489
Type of Manuscript:  PAPER
Category: Coding Theory
Keyword: 
block codessoft decisionmaximum likelihood decodingA* algorithmdual codes
 Summary | Full Text:PDF(219.3KB)