Makoto SUGIHARA


Minimization of the Fabrication Cost for a Bridged-Bus-Based TDMA System under Hard Real-Time Constraints
Makoto SUGIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12  pp. 3041-3051
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Network
Keyword: 
bridged busesfabrication costschedulingtime division multiple accessFlexRay
 Summary | Full Text:PDF(845.6KB)

A Dynamic Continuous Signature Monitoring Technique for Reliable Microprocessors
Makoto SUGIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 477-486
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
soft errorNBTISEUSETcontrol signal errorcontinuous signature monitoringreliabilityvulnerabilitymicroprocessor
 Summary | Full Text:PDF(485.3KB)

On Synthesizing a Reliable Multiprocessor for Embedded Systems
Makoto SUGIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2560-2569
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
heterogeneous multiprocessor synthesissoft errorsingle event upsetreliabilityreal-time system
 Summary | Full Text:PDF(506.4KB)

Character-Size Optimization for Reducing the Number of EB Shots of MCC Lithographic Systems
Makoto SUGIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 631-639
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Manufacturing Technology
Keyword: 
maskless lithographycharacter projectionvariable-shaped beammulti-column-cell systemcharacter size optimizationEB shots
 Summary | Full Text:PDF(587.3KB)

Reliability Inherent in Heterogeneous Multiprocessor Systems and Task Scheduling for Ameliorating Their Reliability
Makoto SUGIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 1121-1128
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
soft errorsingle event upsetreliabilitytask schedulingheterogeneous multiprocessor systems
 Summary | Full Text:PDF(337.4KB)

Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems
Makoto SUGIHARA Yusuke MATSUNAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3451-3460
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
maskless lithographymulti-column-cellscharacter projectionvariable-shaped beamthroughput
 Summary | Full Text:PDF(754.9KB)

Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems
Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 410-417
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
single event upsetSRAMDRAMreliabilitycache architecturetask scheduling
 Summary | Full Text:PDF(558.2KB)

Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems
Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1983-1991
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Design Technology
Keyword: 
soft errorreliabilityestimationcomputer systemsinstruction-set simulation
 Summary | Full Text:PDF(670.7KB)

Technology Mapping Technique for Increasing Throughput of Character Projection Lithography
Makoto SUGIHARA Kenta NAKAMURA Yusuke MATSUNAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 1012-1020
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Lithography-Related Techniques
Keyword: 
maskless lithographycharacter projectionvariable-shaped beamtechnology mappingthroughput
 Summary | Full Text:PDF(715.6KB)

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment
Makoto SUGIHARA Taiga TAKATA Kenta NAKAMURA Ryoichi INANAMI Hiroaki HAYASHI Katsumi KISHIMOTO Tetsuya HASEBE Yukihiro KAWANO Yusuke MATSUNAGA Kazuaki MURAKAMI Katsuya OKUMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 377-383
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: CAD
Keyword: 
cell librarycharacter projectionelectron beamEB shotsthroughputoptimizationinteger linear programming
 Summary | Full Text:PDF(427.7KB)

Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints
Makoto SUGIHARA Kazuaki MURAKAMI Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3174-3184
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
core-based designSOCTAMtest architecturefloorplantest scheduling
 Summary | Full Text:PDF(332.4KB)

Optimization of Test Accesses with a Combined BIST and External Test Scheme
Makoto SUGIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2731-2738
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
test timeBISTexternal testCBETtest schedulingtest accesstest busexternal pins
 Summary | Full Text:PDF(720KB)

Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores
Vikram IYENGAR Hiroshi DATE Makoto SUGIHARA Krishnendu CHAKRABARTY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2632-2638
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Protection
Keyword: 
core partitioningembedded core testingintellectual propertypartially-mergeable corestest access mechanism (TAM)
 Summary | Full Text:PDF(531.4KB)

A Test Methodology for Core-Based System LSIs
Makoto SUGIHARA Hiroshi DATE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2640-2645
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
testing timecore-based system LSIBISTexternal testing
 Summary | Full Text:PDF(584.1KB)