Makoto IKEDA


An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field
Hiromitsu AWANO Tadayuki ICHIHASHI Makoto IKEDA 
Publication:   
Publication Date: 2019/01/01
Vol. E102-A  No. 1  pp. 56-64
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: 
Keyword: 
pairing based cryptographyhardware securityASICoptimal-ate pairinginstruction scheduling optimization
 Summary | Full Text:PDF(2.7MB)

Low Latency 256-bit $mathbb{F}_p$ ECDSA Signature Generation Crypto Processor
Shotaro SUGIYAMA Hiromitsu AWANO Makoto IKEDA 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12  pp. 2290-2296
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ECDSAV2X communicationHardware securityASICscalar multiplication
 Summary | Full Text:PDF(1.9MB)

FOREWORD
Fumio ARAKAWA Makoto IKEDA 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 221-222
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(122.9KB)

Montgomery Multiplier Design for ECDSA Signature Generation Processor
Masato TAMURA Makoto IKEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2444-2452
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ECDSApipelined Montgomery multiplieroptimization
 Summary | Full Text:PDF(1.6MB)

FOREWORD
Makoto IKEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2301-2301
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(230KB)

FOREWORD
Fumio ARAKAWA Makoto IKEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/08/01
Vol. E99-C  No. 8  pp. 899-900
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(132.2KB)

FOREWORD
Fumio ARAKAWA Makoto IKEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 534-535
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(107KB)

A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing
Rimon IKENO Takashi MARUYAMA Satoshi KOMATSU Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/08/01
Vol. E97-A  No. 8  pp. 1688-1698
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Electron Beam Direct WritingCharacter ProjectionroutinginterconnectVIA
 Summary | Full Text:PDF(2.3MB)

High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters
Rimon IKENO Takashi MARUYAMA Satoshi KOMATSU Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2458-2466
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
electron beam direct writingcharacter projectionVIAinterconnectrouting
 Summary | Full Text:PDF(2.1MB)

Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments
Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 518-527
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
self synchronousgate-levelrobustnesssingle event upsetlow voltagereliability
 Summary | Full Text:PDF(6.1MB)

On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems
Jinmyoung KIM Toru NAKURA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 560-567
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
DVSfast voltage hoppingresonant supply noisedecoupling capacitornoise reductioncapacitance boosting
 Summary | Full Text:PDF(2.3MB)

All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction
Sanad BUSHNAQ Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2234-2241
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
all-digitalsub-samplingerror correction
 Summary | Full Text:PDF(1.7MB)

3-D Range Map Acquisition System Based on CMOS Image Sensor Using Time-Multiplexing Structured Pattern
Hiroki YABE Makoto IKEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 635-642
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
structured lightCMOS image sensor
 Summary | Full Text:PDF(2.4MB)

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 643-650
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
resonant supply noiseswitched parasitic capacitorssleep blockpower gating
 Summary | Full Text:PDF(2.3MB)

Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling
Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 546-554
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
power gatinggate-levelpipelineself synchronousenergy minimum operationFPGA
 Summary | Full Text:PDF(4.2MB)

1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
Shingo MANDAI Tetsuya IIZUKA Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6  pp. 1098-1104
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
time-to-digital converterTDCtime-difference-amplifierTDAtime amp
 Summary | Full Text:PDF(1.3MB)

On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 511-519
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
power supply noiseresonanceparasitic capacitancesleep blockDVSpower gating
 Summary | Full Text:PDF(1.7MB)

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
Tetsuya IIZUKA Jaehyun JEONG Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 487-494
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
process variabilityall digitalon-chip monitorbuffer ringNBTIPBTI
 Summary | Full Text:PDF(1.1MB)

Cascaded Time Difference Amplifier with Differential Logic Delay Cell
Shingo MANDAI Toru NAKURA Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 654-662
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
time-difference-amplifierTDAtime amp
 Summary | Full Text:PDF(888.9KB)

Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method
Shingo MANDAI Taihei MOMMA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/01/01
Vol. E94-C  No. 1  pp. 124-127
Type of Manuscript:  BRIEF PAPER
Category: Microwaves, Millimeter-Waves
Keyword: 
3-Daddress compressionimage sensorrange-finderlight-sectionrow-parallel
 Summary | Full Text:PDF(942.4KB)

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment
Benjamin STEFAN DEVLIN Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7  pp. 1319-1328
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
self synchronousfpgapipeline alignmentlow powerhigh throughputdynamic logicdual pipeline
 Summary | Full Text:PDF(6.3MB)

Time Difference Amplifier with Robust Gain Using Closed-Loop Control
Toru NAKURA Shingo MANDAI Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 303-308
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
time difference amplifierTDAtime to digital converterTDCvoltage controlled delay line
 Summary | Full Text:PDF(636.1KB)

Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
Shingo MANDAI Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6  pp. 798-805
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
image sensorlight-section methodstereo-matchingdual imager coremulti functional range finder
 Summary | Full Text:PDF(1.5MB)

A Structural Approach for Transistor Circuit Synthesis
Hiroaki YOSHIDA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3529-3537
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
transistor-level synthesisstatic CMOS circuitsalgebraic transformationsstructural transformationsdynamic programming
 Summary | Full Text:PDF(448.3KB)

LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil
Taisuke KAZAMA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3546-3550
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
character projection (CP)electron beam direct writing (EBDW)combined cell stencil (CCS)placement & routing
 Summary | Full Text:PDF(584.7KB)

Autonomous di/dt Control of Power Supply for Margin Aware Operation
Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1689-1694
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
autonomous di/dt controlmargin awaredi/dt detectorpower supply current
 Summary | Full Text:PDF(840.6KB)

Noise Immunity Investigation of Low Power Design Schemes
Mohamed ABBAS Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/08/01
Vol. E89-C  No. 8  pp. 1238-1247
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
noise immunitylow powerpower supply noisedigital design
 Summary | Full Text:PDF(626.6KB)

On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function
Mohamed ABBAS Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 370-376
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Signal Integrity and Variability
Keyword: 
on-chip detectornon-periodic noisehigh-swing noise
 Summary | Full Text:PDF(590.1KB)

Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply
Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 364-369
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Signal Integrity and Variability
Keyword: 
substrate noisedi/dtfeedforward active cancellinganti-phaseground bouncedi/dt detector
 Summary | Full Text:PDF(673.2KB)

Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3485-3491
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
exact minimum-width transistor placementBoolean Satisfiabilitynon-dual CMOS cells
 Summary | Full Text:PDF(265.8KB)

Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs
Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8  pp. 1734-1739
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category: 
Keyword: 
stubon-boardpower supply noisedi/dt noisePRBS pattern
 Summary | Full Text:PDF(704.7KB)

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/07/01
Vol. E88-A  No. 7  pp. 1957-1963
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
comprehensive cell layout synthesisCMOS logic cellcritical areadefect sensitivityyield optimization
 Summary | Full Text:PDF(408.6KB)

A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells
Ulkuhan EKINCIEL Hiroaki YAMAOKA Hiroaki YOSHIDA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/06/01
Vol. E88-D  No. 6  pp. 1159-1167
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
PLAmodule generatorcell generationHDL behavior generation
 Summary | Full Text:PDF(1MB)

On-Chip di/dt Detector Circuit
Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5  pp. 782-787
Type of Manuscript:  Special Section PAPER (Special Section on Microelectronic Test Structures)
Category: 
Keyword: 
di/dt detectormutual inductorspiral inductorparasitic inductancepower supply noise
 Summary | Full Text:PDF(555.8KB)

Stub vs. Capacitor for Power Supply Noise Reduction
Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/01/01
Vol. E88-C  No. 1  pp. 125-132
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
stubdecoupling capacitorpower supply noisedi/dt noiseIR drop
 Summary | Full Text:PDF(407.7KB)

Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition
Yusuke OIKE Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/12/01
Vol. E87-C  No. 12  pp. 2164-2171
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
image sensorpixel-level color imagingmodulated RGB flashlightobject extractiontime-of-flight range findingimage recognition
 Summary | Full Text:PDF(1.4MB)

High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3293-3300
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
high speedcell layout synthesisBoolean SatisfiabilitySATCMOS logic cellminimum width
 Summary | Full Text:PDF(511.5KB)

Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories
Yusuke OIKE Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1847-1855
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
associative memorycontent addressable memoryCAMHamming distancecapacity scalabilitymulti-chip structure
 Summary | Full Text:PDF(1.5MB)

A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits
Hiroaki YAMAOKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6  pp. 1069-1077
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLAhigh-speedarea-efficientdual-rail
 Summary | Full Text:PDF(1.5MB)

A Logic-Cell-Embedded PLA (LCPLA): An Area-Efficient Dual-Rail Array Logic Architecture
Hiroaki YAMAOKA Hiroaki YOSHIDA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/02/01
Vol. E87-C  No. 2  pp. 238-245
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLAlogic celldual-railarray logicarea-efficient
 Summary | Full Text:PDF(585.8KB)

A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method
Yusuke OIKE Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/11/01
Vol. E86-C  No. 11  pp. 2320-2328
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
position detectorsmart image sensorhigh speedrow-parallel architecture3-D camera
 Summary | Full Text:PDF(1.2MB)

High-Sensitivity and Wide-Dynamic-Range Position Sensor Using Logarithmic-Response and Correlation Circuit
Yusuke OIKE Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8  pp. 1651-1658
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
position sensorhigh sensitivitywide dynamic rangelogarithmic responsecorrelation
 Summary | Full Text:PDF(1MB)

A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
Hiroaki YAMAOKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/09/01
Vol. E84-C  No. 9  pp. 1240-1246
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
high speedPLAarray logic circuitsense amplifier
 Summary | Full Text:PDF(949.8KB)

Approaches for Reducing Power Consumption in VLSI Bus Circuits
Kunihiro ASADA Makoto IKEDA Satoshi KOMATSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 153-160
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
low powerreduced signal swingsignal transition reductionbus encoding/decodingtime-domain circuitminimum Hamming-distance detector
 Summary | Full Text:PDF(1.4MB)

Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors
Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/25
Vol. E79-C  No. 3  pp. 424-429
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
low powerpartitioned-bus architecturevariable-width-bus schememicroprocessor
 Summary | Full Text:PDF(513.1KB)

Data Bypassing Register File for Low Power Microprocessor
Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/10/25
Vol. E78-C  No. 10  pp. 1470-1472
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
low powerdata bypassing register filemicroprocessorimplicit data bypassing scheme
 Summary | Full Text:PDF(259.9KB)

A Proposal of High Speed and Low Power Data Transmission Method for VLSIs by Reduced-Swing Signal
Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1666-1675
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
 Summary | Full Text:PDF(649.9KB)

Analytical Modeling of Dynamic Performance of Deep Sub-micron SOI/SIMOX Based on Current-Delay Product
Minoru FUJISHIMA Makoto IKEDA Kunihiro ASADA Yasuhisa OMURA Katsutoshi IZUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/12/25
Vol. E75-C  No. 12  pp. 1506-1514
Type of Manuscript:  Special Section PAPER (Special Issue on SOI (Si on Insulator) Devices)
Category: Deep Sub-micron SOI CMOS
Keyword: 
CMOSSOIdeep-submicronmodelingring oscillator
 Summary | Full Text:PDF(646.4KB)