Kunihiro KOMIYAJI


A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM
Hideharu YAHATA Yoji NISHIO Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Atsushi HIRAISHI Yoshitaka KINOSHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 557-565
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
CMOShigh speedcache SRAMchip floor plansense amplifieroutput registersetup/hold time
 Summary | Full Text:PDF(633.1KB)

A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers
Koichiro ISHIBASHI Koichi TAKASUGI Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Toshiaki YAMANAKA Akira FUKAMI Naotaka HASHIMOTO Nagatoshi OHKI Akihiro SHIMIZU Takashi HASHIMOTO Takahiro NAGANO Takashi NISHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/06/25
Vol. E78-C  No. 6  pp. 728-734
Type of Manuscript:  Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
Category: 
Keyword: 
 Summary | Full Text:PDF(646.7KB)

A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers
Koichiro ISHIBASHI Kunihiro KOMIYAJI Sadayuki MORITA Toshiro AOTO Shuji IKEDA Kyoichiro ASAYAMA Atsuyosi KOIKE Toshiaki YAMANAKA Naotaka HASHIMOTO Haruhito IIDA Fumio KOJIMA Koichi MOTOHASHI Katsuro SASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 741-748
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
 Summary | Full Text:PDF(683.1KB)