Kuniaki KOYAMA


Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM
Yoshiharu AIMOTO Tohru KIMURA Yoshikazu YABE Hideki HEIUCHI Youetsu NAKAZAWA Masato MOTOMURA Takuya KOGA Yoshihiro FUJITA Masayuki HAMADA Takaho TANIGAWA Hajime NOBUSAWA Kuniaki KOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 759-767
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
integration of DRAM and logicembedded DRAMlow powerhigh memory bandwidth
 Summary | Full Text:PDF(951.7KB)

Effects of Field Edge Steps on Electrical Gate Linewidth Measurements
Naoki KASAI Ichiro YAMAMOTO Koji URABE Kuniaki KOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2  pp. 152-157
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Device and Circuit Characterization
Keyword: 
test structureMOSFETlinewidthfield step
 Summary | Full Text:PDF(798KB)