IEICE SEARCH SYSTEM

Kozo KINOSHITA

A Novel ATPG Method for Capture Power Reduction during Scan Testing Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Tatsuya SUZUKI Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/09/01 Vol. E90-D No. 9 pp. 1398-1405 Type of Manuscript: PAPER Category: Dependable Computing Keyword: scan testing, capture power, X-bit, IR-drop,
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A Per-Test Fault Diagnosis Method Based on the X-Fault Model Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Yuta YAMATO Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/11/01 Vol. E89-D No. 11 pp. 2756-2765 Type of Manuscript: PAPER Category: Dependable Computing Keyword: fault diagnosis, per-test, X-fault model,
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A New Method for Low-Capture-Power Test Generation for Scan Testing Xiaoqing WEN Yoshiyuki YAMASHITA Seiji KAJIHARA Laung-Terng WANG Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/05/01 Vol. E89-D No. 5 pp. 1679-1686 Type of Manuscript: PAPER Category: Dependable Computing Keyword: scan testing, capture power, X-bit, IR-drop,
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On Design for I_DDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/04/01 Vol. E88-D No. 4 pp. 703-710 Type of Manuscript: PAPER Category: Computer Components Keyword: fault diagnosis, I_DDQ, transistor leakage fault model, multiple power supply, circuit partitioning,
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Reduction of the Target Fault List and Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits Kazuya SHIMIZU Takanori SHIRAI Masaya TAKAMURA Noriyoshi ITAZAKI Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1526-1533 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test and Diagnosis for Timing Faults Keyword: domino circuit, crosstalk fault, target fault reduction, fault simulation,
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IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates Masaki HASHIZUME Teppei TAKEDA Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Yukiya MIURA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1534-1541 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Current Test Keyword: IDDQ sensor, CMOS, IDDQ test, bridging fault,
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Analysis of I_DDQ Occurrence in Testing Arabi KESHK Yukiya MIURA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/04/01 Vol. E84-D No. 4 pp. 534-536 Type of Manuscript: LETTER Category: Computer System Element Keyword: I_DDQ testing, bridging fault, fault analysis,
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On Processing Order for Obtaining Implication Relations in Static Learning Hideyuki ICHIHARA Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/10/20 Vol. E83-D No. 10 pp. 1908-1911 Type of Manuscript: LETTER Category: Fault Tolerance Keyword: test generation, implication, static learning,
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Power Estimation and Reduction of CMOS Circuits Considering Gate Delay Hiroaki UEDA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/01/20 Vol. E82-D No. 1 pp. 301-308 Type of Manuscript: PAPER Category: Computer Systems Keyword: CMOS circuit, low power design, gate delay, transition probability, switching activity,
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Test Generation for Sequential Circuits under IDDQ Testing Toshiyuki MAEDA Yoshinobu HIGAMI Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/20 Vol. E81-D No. 7 pp. 689-696 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: IDDQ Testing Keyword: sequential circuit, test generation, IDDQ testing, bridging fault,
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Logic Optimization: Redundancy Addition and Removal Using Implication Relations Hideyuki ICHIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/20 Vol. E81-D No. 7 pp. 724-730 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Logic Simulation and Logic Optimization Keyword: logic optimization, implication, redundancy identification,
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Transistor Leakage Fault Diagnosis for CMOS Circuits Xiaoqing WEN Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/20 Vol. E81-D No. 7 pp. 697-705 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Fault Diagnosis Keyword: fault diagnosis, transistor leakage fault, I_DDQ, primary output, fault simulation, diagnostic test generation,
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Transistor Leakage Fault Diagnosis with I_DDQ and Logic Information Wen XIAOQING Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/04/20 Vol. E81-D No. 4 pp. 372-381 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: fault diagnosis, transistor leakage fault, I_DDQ testing, fault simulation, diagnostic vector generation,
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A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits Noriyoshi ITAZAKI Yasutaka IDOMOTO Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/01/20 Vol. E80-D No. 1 pp. 38-43 Type of Manuscript: Special Section PAPER (Special Issue on Fault-Tolerant Computing) Category: Testing/Checking Keyword: crosstalk fault, fault simulation, sequential circuit, test,
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Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement Hiroyuki YOTSUYANAGI Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/20 Vol. E78-D No. 7 pp. 861-867 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: retiming, logic synthesis, redundancy removal, test synthesis,
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Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis Seiji KAJIHARA Rikiya NISHIGAYA Tetsuji SUMIOKA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/20 Vol. E78-D No. 7 pp. 811-816 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: test generation, multiple stuck-at fault, vector pair analysis, combinational circuit,
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Testing of k-FR Circuits under Highly Observable Condition Xiaoqing WEN Hideo TAMAMOTO Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/20 Vol. E78-D No. 7 pp. 830-838 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: testable design, fault testing, highly observable condition, circuit conversion,
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Efficient Guided-Probe Fault Location Method for Sequential Circuits Xiaoging WEN Kozo KINOSHITA Hideo TAMAMOTO Hiroshi YOKOYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/02/20 Vol. E78-D No. 2 pp. 122-129 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: guided-probe fault location, selection of lines to probe, sequential circuit, VLSI diagnosis,
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A Reduced Scan Shift Method for Sequential Circuit Testing Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/20 Vol. E77-A No. 12 pp. 2010-2016 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: sequential circuit, test generation, design for testability, scan circuit, reduced scan shift,
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Traffic Analysis of the Stop-and-Wait ARQ over A Markov Error Channel Masaharu KOMATSU Chun-Xiang CHEN Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1994/04/20 Vol. E77-B No. 4 pp. 477-484 Type of Manuscript: PAPER Category: Communication Theory Keyword: queueing analysis, stop-and-wait ARQ, dependent error,
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Throughput Analysis of ARQ Schemes in Dialogue Communication over Half-Duplex Line Chun-Xiang CHEN Masaharu KOMATSU Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1994/04/20 Vol. E77-B No. 4 pp. 485-493 Type of Manuscript: PAPER Category: Communication Theory Keyword: throughput, ARQ scheme, half-duplex line, dialogue communication,
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Channel-Grouping Methods on Go-Back-N ARQ Scheme in Multiple-Parallel-Channel System Chun-Xiang CHEN Masaharu KOMATSU Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1994/02/20 Vol. E77-B No. 2 pp. 265-269 Type of Manuscript: LETTER Category: Communication Theory Keyword: channel-grouping methods, throughput, ARQ scheme, multiple-channel system,
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Throughput Performances of ARQ Protocols Operating over Generalized Two-State Markov Error Channel Masaharu KOMATSU Yukuo HAYASHIDA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1994/01/20 Vol. E77-B No. 1 pp. 35-42 Type of Manuscript: PAPER Category: Communication Theory Keyword: throughput, ARQ protocol, Markov error channel, dependent error,
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Test Sequence Generation for Sequential Circuits with Distinguishing Sequences Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/20 Vol. E76-A No. 10 pp. 1730-1737 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: distinguishing sequence, stuck-at fault, sequential circuit, test sequence generation, design rechnique,
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Consecutive Customer Loss Phenomenon due to Buffer Overflow in Finite Buffer Queueing System Masaharu KOMATSU Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/20 Vol. E76-A No. 10 pp. 1781-1789 Type of Manuscript: PAPER Category: Queueing Theory Keyword: modeling and simulation, wueueing theory,
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FOREWORD Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/20 Vol. E76-D No. 7 pp. 737-738 Type of Manuscript: FOREWORD Category: Keyword:
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Efficient Methods for Guided-Probe Diagnosis WEN Xiaoqing Noriyoshi ITAZAKI Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/20 Vol. E76-D No. 7 pp. 817-825 Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: guided-probe diagnosis, E-beam probing, probing line determination method, fault probability,
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Synthesis of Testable Sequential Circuits with Reduced Checking Sequences Satoshi SHIBATANI Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/20 Vol. E76-D No. 7 pp. 739-746 Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: sequential circuit, design for testability, automated logic synthesis, checking sequence, state assignment,
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Performance Evaluation of Block SR-ARQ Scheme in High-Speed Communication Environments Chunxiang CHEN Masaharu KOMATSU Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1992/12/20 Vol. E75-B No. 12 pp. 1338-1345 Type of Manuscript: Special Section PAPER (Special Issue on Teletraffic) Category: Keyword: block SR-ARQ scheme, high-speed communication environments, throughput, packet delay,
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A Testable Design of Sequential Circuits under Highly Observable Condition WEN Xiaoqing Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/05/20 Vol. E75-D No. 3 pp. 334-341 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: design for testability, highly observable testing, fault diagnosis, sequential circuit, circuit modification,
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Testable Design for Stuck-Open Faults with the Robustness Yukiya MIURA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1990/08/20 Vol. E73-E No. 8 pp. 1294-1300 Type of Manuscript: Special Section PAPER (Special Issue on Fault-Tolerant Systems) Category: Keyword:
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FOREWORD Kozo KINOSHITA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1990/08/20 Vol. E73-E No. 8 pp. 1245-1246 Type of Manuscript: FOREWORD Category: Keyword:
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