Koji TANAKA


Formal Verification of Totally Self-Checking Properties of Combinational Circuits
Kazuo KAWAKUBO Koji TANAKA Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1  pp. 57-62
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Verification
Keyword: 
formal verificationtotally self-checkingfault tolerancebinary decision diagram
 Summary | Full Text:PDF(508.2KB)

Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
Tadaaki YAMAUCHI Koji TANAKA Kiyohiro FURUTANI Yoshikazu MOROOKA Hiroshi MIYAMOTO Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 858-865
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
self-timing data-bustiming delaydevice fluctuationamplifier64-Mb DRAMs
 Summary | Full Text:PDF(782.8KB)

VLSI Systolic Array for SRIF Digital Signal Processing Algorithm
Kazuhiko IWAMI Koji TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/09/25
Vol. E77-A  No. 9  pp. 1475-1483
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from the 8th Digital Signal Processing Symposium)
Category: Digital Signal Processing Hardware
Keyword: 
digital signal processingparallel signal processingVLSI design technology
 Summary | Full Text:PDF(675.9KB)