Koji INOUE


Parallel Precomputation with Input Value Prediction for Model Predictive Control Systems
Satoshi KAWAKAMI Takatsugu ONO Toshiyuki OHTSUKA Koji INOUE 
Publication:   
Publication Date: 2018/12/01
Vol. E101-D  No. 12  pp. 2864-2877
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Real-time Systems
Keyword: 
parallel precomputationinput value predictionapproximate computingmodel predictive controlreal-time system
 Summary | Full Text:PDF(1.6MB)

Real-Time Frame-Rate Control for Energy-Efficient On-Line Object Tracking
Yusuke INOUE Takatsugu ONO Koji INOUE 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12  pp. 2297-2307
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
object trackinglow energyframe-rate optimization
 Summary | Full Text:PDF(3.1MB)

Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs
Satoshi IMAMURA Yuichiro YASUI Koji INOUE Takatsugu ONO Hiroshi SASAKI Katsuki FUJISAWA 
Publication:   
Publication Date: 2018/09/01
Vol. E101-D  No. 9  pp. 2247-2257
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
DRAMaddress mapping schemesenergy efficiency
 Summary | Full Text:PDF(1.1MB)

Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing
Koki ISHIDA Masamitsu TANAKA Takatsugu ONO Koji INOUE 
Publication:   
Publication Date: 2018/05/01
Vol. E101-C  No. 5  pp. 359-369
Type of Manuscript:  INVITED PAPER (Special Section on Innovative Superconducting Devices Based on New Physical Phenomena)
Category: 
Keyword: 
single flux quantum (SFQ)cryogenic computingmicroprocessorcache memoryJosephson junctionlow-powerhigh-performanceenergy-efficient
 Summary | Full Text:PDF(1.3MB)

An Inter-Prediction Method Using Sparse Representation for High Efficiency Video Coding
Koji INOUE Kohei ISECHI Hironobu SAITO Yoshimitsu KUROKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/11/01
Vol. E96-A  No. 11  pp. 2191-2193
Type of Manuscript:  Special Section LETTER (Special Section on Smart Multimedia & Communication Systems)
Category: Image Processing
Keyword: 
inter predictionhigh efficiency video codingsparse representation
 Summary | Full Text:PDF(371.5KB)

Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs
Junya KAIDA Yuko HARA-AZUMI Takuji HIEDA Ittetsu TANIGUCHI Hiroyuki TOMIYAMA Koji INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/10/01
Vol. E96-D  No. 10  pp. 2268-2271
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
many-core SoCsapplication mappingsystem-level designembedded systems
 Summary | Full Text:PDF(592.4KB)

A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards
Son-Truong NGUYEN Masaaki KONDO Tomoya HIRAO Koji INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1645-1653
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
many-core processorevaluation platformprototypingFPGA
 Summary | Full Text:PDF(1.3MB)

A Linear Manifold Color Descriptor for Medicine Package Recognition
Kenjiro SUGIMOTO Koji INOUE Yoshimitsu KUROKI Sei-ichiro KAMATA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/05/01
Vol. E95-D  No. 5  pp. 1264-1271
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Multimedia Signal Processing Techniques and Applications)
Category: Image Processing
Keyword: 
low-level color descriptorlinear manifoldmedicine package recognition
 Summary | Full Text:PDF(1.8MB)

NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers
Hideki MIWA Ryutaro SUSUKITA Hidetomo SHIBAMURA Tomoya HIRAO Jun MAKI Makoto YOSHIDA Takayuki KANDO Yuichiro AJIMA Ikuo MIYOSHI Toshiyuki SHIMIZU Yuji OINAGA Hisashige ANDO Yuichi INADOMI Koji INOUE Mutsumi AOYAGI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/12/01
Vol. E94-D  No. 12  pp. 2298-2308
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
discrete event simulationmultiprocessor interconnectionparallel processing
 Summary | Full Text:PDF(1.5MB)

Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
Farhad MEHDIPOUR Hamid NOORI Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3182-3192
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
reconfigurable instruction-set processoranalytical modelingdesign space explorationdata flow graph accelerator
 Summary | Full Text:PDF(1009.8KB)

Reducing On-Chip DRAM Energy via Data Transfer Size Optimization
Takatsugu ONO Koji INOUE Kazuaki MURAKAMI Kenji YOSHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 433-443
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
low powervariable line-sizeon-chip DRAMhigh bandwidthembedded systems
 Summary | Full Text:PDF(497.8KB)

A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions
Hamid NOORI Farhad MEHDIPOUR Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 497-508
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
custom instructionsextensible processorreconfigurable functional unitconditional execution
 Summary | Full Text:PDF(1.5MB)

Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems
Hamid NOORI Maziar GOUDARZI Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 418-431
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
temperature-aware designcache memoryleakage currentlow energyembedded systems
 Summary | Full Text:PDF(1.7MB)

Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits
Naofumi TAKAGI Kazuaki MURAKAMI Akira FUJIMAKI Nobuyuki YOSHIKAWA Koji INOUE Hiroaki HONDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/03/01
Vol. E91-C  No. 3  pp. 350-355
Type of Manuscript:  INVITED PAPER (Special Section on Recent Progress in Superconductive Digital Electronics)
Category: 
Keyword: 
superconductorrapid single-flux-quantum circuitreconfigurable data-pathhigh-performance computingsupercomputer
 Summary | Full Text:PDF(297.2KB)

Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs
Farhad MEHDIPOUR Hamid NOORI Morteza SAHEB ZAMANI Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12  pp. 1956-1966
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable Device and Design Tools
Keyword: 
reconfigurable acceleratorconditional executioncontrol data flow graphtemporal partitioningreconfigurable processor
 Summary | Full Text:PDF(1.5MB)

A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips
Mariko SAKAMOTO Akira KATSUNO Go SUGIZAKI Toshio YOSHIDA Aiichiro INOUE Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1972-1982
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Architecture for Communication/Server Systems
Keyword: 
enterprise server systemcache coherencedistributed shared memoryonline transaction processingperformance evaluation
 Summary | Full Text:PDF(4.9MB)

Return Address Protection on Cache Memories
Koji INOUE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/12/01
Vol. E89-C  No. 12  pp. 1937-1947
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
low energysecuritycachebuffer overflowstack smashing
 Summary | Full Text:PDF(1.6MB)

Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy
Hidekazu TANAKA Koji INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3274-3281
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword: 
low powercacheway predictionconfidence information
 Summary | Full Text:PDF(1MB)

Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 862-868
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low powercacheleakage
 Summary | Full Text:PDF(1014.7KB)

Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4  pp. 799-805
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low powerinstruction ROMembedded systemsencoding
 Summary | Full Text:PDF(710.3KB)

Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 279-287
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
cachelow powerlook uprun time
 Summary | Full Text:PDF(726.5KB)

Trends in High-Performance, Low-Power Cache Memory Architectures
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 304-314
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
cachelow powerhigh performancemicroprocessorsurvey
 Summary | Full Text:PDF(238.5KB)

A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11  pp. 1716-1723
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
cachelow powervariable line-sizemerged DRAM/logic LSIshigh bandwidth
 Summary | Full Text:PDF(1001.2KB)

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Vol. E83-D  No. 5  pp. 1048-1057
Type of Manuscript:  PAPER
Category: Computer System Element
Keyword: 
cachevariable line-sizemerged DRAM/logic LSIshigh bandwidth
 Summary | Full Text:PDF(1015.7KB)

A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection
Koji INOUE Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 186-194
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
cachelow powerlow energyway predictionhigh performance
 Summary | Full Text:PDF(1015.4KB)

High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1438-1447
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
cachemerged DRAM/logic LSIsmemory system
 Summary | Full Text:PDF(938.1KB)