IEICE SEARCH SYSTEM

Koichiro MASHIKO

A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm Hao SAN Yoshitaka JINGU Hiroki WADA Hiroyuki HAGIWARA Akira HAYAKAWA Haruo KOBAYASHI Tatsuji MATSUURA Kouichi YAHAGI Junya KUDOH Hideo NAKANE Masao HOTTA Toshiro TSUKADA Koichiro MASHIKO Atsushi WADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1181-1188 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: complex bandpass ΔΣAD modulator, I, Q path mismatches, dynamic matching, miltibit, data-weighted averaging,
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Complex Bandpass ΔΣAD Modulator Architecture without I, Q-Path Crossing Layout Hao SAN Akira HAYAKAWA Yoshitaka JINGU Hiroki WADA Hiroyuki HAGIWARA Kazuyuki KOBAYASHI Haruo KOBAYASHI Tatsuji MATSUURA Kouichi YAHAGI Junya KUDOH Hideo NAKANE Masao HOTTA Toshiro TSUKADA Koichiro MASHIKO Atsushi WADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 908-915 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: complex bandpass ΔΣAD modulator, I, Q path mismatches, dynamic matching, multiplexer,
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High-Speed Continuous-Time Subsampling Bandpass ΔΣ AD Modulator Architecture Employing Radio Frequency DAC Masafumi UEMORI Haruo KOBAYASHI Tomonari ICHIKAWA Atsushi WADA Koichiro MASHIKO Toshiro TSUKADA Masao HOTTA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 916-923 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: continuous-time, subsampling, bandpass, ΔΣ modulator, RF DAC, jitter,
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Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application Yasuo YAMAGUCHI Takashi IPPOSHI Kimio UEDA Koichiro MASHIKO Shigeto MAEGAWA Masahide INUISHI Tadashi NISHIMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/12/01 Vol. E84-C No. 12 pp. 1735-1745 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Systems with New Concepts) Category: Keyword: SOI, SOC, partially depleted, isolation,
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Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits Koichiro MASHIKO Kimio UEDA Tsutomu YOSHIMURA Takanori HIROTA Yoshiki WADA Jun TAKASOH Kazuo KUBO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/11/20 Vol. E83-C No. 11 pp. 1697-1704 Type of Manuscript: INVITED PAPER (Special Issue on Low-power LSIs and Technologies) Category: Keyword: silicon on insulator (SOI), complementary metal oxide semiconductor (CMOS), emitter coupled logic (ECL),
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A CAD-Compatible SOI-CMOS Gate Array Using 0.35µm Partially-Depleted Transistors Kimio UEDA Koji NII Yoshiki WADA Shigenobu MAEDA Toshiaki IWAMATSU Yasuo YAMAGUCHI Takashi IPPOSHI Shigeto MAEGAWA Koichiro MASHIKO Yasutaka HORIBA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/20 Vol. E83-C No. 2 pp. 205-211 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: SOI, CMOS, field-shield isolation, gate array, low-power, high-speed,
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A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme Hiroaki SUZUKI Hiroshi MAKINO Koichiro MASHIKO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/01/20 Vol. E82-C No. 1 pp. 105-110 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: divider, floating-point execution, redundant binary circuits, asynchronous circuit, self-timed circuit,
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A 300 MHz Dual Port Palette RAM Using Port Swap Architecture Yasunobu NAKASE Koichiro MASHIKO Yoshio MATSUDA Takeshi TOKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/20 Vol. E81-C No. 9 pp. 1484-1490 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: dual port SRAM, graphics, color palette, small cell size,
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SOI/CMOS Circuit Design for High-Speed Communication LSIs Kimio UEDA Yoshiki WADA Takanori HIROTA Shigenobu MAEDA Koichiro MASHIKO Hisanori HAMANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/20 Vol. E80-C No. 7 pp. 886-892 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Novel Structure Devices Keyword: multiplexer, demultiplexer, CMOS device, SOI/CMOS device, low-power, high-speed,
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Analysis of the Delay Distributions of 0.5 µm SOI LSIs Toshiaki IWAMATSU Takashi IPPOSHI Yasuo YAMAGUCHI Kimio UEDA Koichiro MASHIKO Shigeto MAEGAWA Yasuo INOUE Tadashi HIRAO Tdashi NISHIMURA Akihiko YASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/03/20 Vol. E80-C No. 3 pp. 464-471 Type of Manuscript: Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies) Category: Keyword: SOI, SIMOX, divider, adder, high-speed, low voltage,
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A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Koichiro MASHIKO Tadashi SUMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/20 Vol. E79-C No. 7 pp. 915-924 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Logic Keyword:
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A Design of High-Speed 4-2 Compressor for Fast Multiplier Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Hirofumi SHINOHARA Koichiro MASHIKO Tadashi SUMI Yasutaka HORIBA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/04/20 Vol. E79-C No. 4 pp. 538-548 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs) Category: Keyword: 4-2 compressor, multiplier, redundant binary, transmission gate, CMOS circuit,
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A 2.6-ns 64-b Fast and Small CMOS Adder Hiroyuki MORINAKA Hiroshi MAKINO Yasunobu NAKASE Hiroaki SUZUKI Koichiro MASHIKO Tadashi SUMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/04/20 Vol. E79-C No. 4 pp. 530-537 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs) Category: Keyword: addition, carry look-ahead adder, binary look-ahead adder, carry select, modified carry select, CMOS, VLSI,
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3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer Kimio UEDA Nagisa SASAKI Hisayasu SATO Shunji KUBO Koichiro MASHIKO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/20 Vol. E78-C No. 7 pp. 866-872 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: multiplexer, demultiplexer, silicon-bipolar, low-power, ECL,
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A New Emitter-Follower Circuit for High-Speed and Low-Power ECL Nagisa SASAKI Hisayasu SATO Kimio UEDA Koichiro MASHIKO Hiroshi SHIBATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/20 Vol. E78-C No. 4 pp. 374-380 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: Digital Circuits Keyword: ECL, emitter-follower circuit, bipolar, high-speed and low-power,
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