Koichiro MASHIKO


A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm
Hao SAN Yoshitaka JINGU Hiroki WADA Hiroyuki HAGIWARA Akira HAYAKAWA Haruo KOBAYASHI Tatsuji MATSUURA Kouichi YAHAGI Junya KUDOH Hideo NAKANE Masao HOTTA Toshiro TSUKADA Koichiro MASHIKO Atsushi WADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/06/01
Vol. E90-C  No. 6  pp. 1181-1188
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
complex bandpass ΔΣAD modulatorIQ path mismatchesdynamic matchingmiltibitdata-weighted averaging
 Summary | Full Text:PDF(1.1MB)

High-Speed Continuous-Time Subsampling Bandpass ΔΣ AD Modulator Architecture Employing Radio Frequency DAC
Masafumi UEMORI Haruo KOBAYASHI Tomonari ICHIKAWA Atsushi WADA Koichiro MASHIKO Toshiro TSUKADA Masao HOTTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 916-923
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
continuous-timesubsamplingbandpassΔΣ modulatorRF DACjitter
 Summary | Full Text:PDF(1.6MB)

Complex Bandpass ΔΣAD Modulator Architecture without I, Q-Path Crossing Layout
Hao SAN Akira HAYAKAWA Yoshitaka JINGU Hiroki WADA Hiroyuki HAGIWARA Kazuyuki KOBAYASHI Haruo KOBAYASHI Tatsuji MATSUURA Kouichi YAHAGI Junya KUDOH Hideo NAKANE Masao HOTTA Toshiro TSUKADA Koichiro MASHIKO Atsushi WADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 908-915
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
complex bandpass ΔΣAD modulatorIQ path mismatchesdynamic matchingmultiplexer
 Summary | Full Text:PDF(820.3KB)

Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application
Yasuo YAMAGUCHI Takashi IPPOSHI Kimio UEDA Koichiro MASHIKO Shigeto MAEGAWA Masahide INUISHI Tadashi NISHIMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/12/01
Vol. E84-C  No. 12  pp. 1735-1745
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Systems with New Concepts)
Category: 
Keyword: 
SOISOCpartially depletedisolation
 Summary | Full Text:PDF(1.8MB)

Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits
Koichiro MASHIKO Kimio UEDA Tsutomu YOSHIMURA Takanori HIROTA Yoshiki WADA Jun TAKASOH Kazuo KUBO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11  pp. 1697-1704
Type of Manuscript:  INVITED PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
silicon on insulator (SOI)complementary metal oxide semiconductor (CMOS)emitter coupled logic (ECL)
 Summary | Full Text:PDF(2.1MB)

A CAD-Compatible SOI-CMOS Gate Array Using 0.35µm Partially-Depleted Transistors
Kimio UEDA Koji NII Yoshiki WADA Shigenobu MAEDA Toshiaki IWAMATSU Yasuo YAMAGUCHI Takashi IPPOSHI Shigeto MAEGAWA Koichiro MASHIKO Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 205-211
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
SOICMOSfield-shield isolationgate arraylow-powerhigh-speed
 Summary | Full Text:PDF(2MB)

A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme
Hiroaki SUZUKI Hiroshi MAKINO Koichiro MASHIKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/01/25
Vol. E82-C  No. 1  pp. 105-110
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
dividerfloating-point executionredundant binary circuitsasynchronous circuitself-timed circuit
 Summary | Full Text:PDF(384.2KB)

A 300 MHz Dual Port Palette RAM Using Port Swap Architecture
Yasunobu NAKASE Koichiro MASHIKO Yoshio MATSUDA Takeshi TOKUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1484-1490
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
dual port SRAMgraphicscolor palettesmall cell size
 Summary | Full Text:PDF(729.6KB)

SOI/CMOS Circuit Design for High-Speed Communication LSIs
Kimio UEDA Yoshiki WADA Takanori HIROTA Shigenobu MAEDA Koichiro MASHIKO Hisanori HAMANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 886-892
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Novel Structure Devices
Keyword: 
multiplexerdemultiplexerCMOS deviceSOI/CMOS devicelow-powerhigh-speed
 Summary | Full Text:PDF(558.1KB)

Analysis of the Delay Distributions of 0.5 µm SOI LSIs
Toshiaki IWAMATSU Takashi IPPOSHI Yasuo YAMAGUCHI Kimio UEDA Koichiro MASHIKO Shigeto MAEGAWA Yasuo INOUE Tadashi HIRAO Tdashi NISHIMURA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C  No. 3  pp. 464-471
Type of Manuscript:  Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: 
Keyword: 
SOISIMOXdivideradderhigh-speedlow voltage
 Summary | Full Text:PDF(735.3KB)

A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Koichiro MASHIKO Tadashi SUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C  No. 7  pp. 915-924
Type of Manuscript:  Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Logic
Keyword: 
 Summary | Full Text:PDF(933.5KB)

A Design of High-Speed 4-2 Compressor for Fast Multiplier
Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Hirofumi SHINOHARA Koichiro MASHIKO Tadashi SUMI Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4  pp. 538-548
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
4-2 compressormultiplierredundant binarytransmission gateCMOS circuit
 Summary | Full Text:PDF(1012.7KB)

A 2.6-ns 64-b Fast and Small CMOS Adder
Hiroyuki MORINAKA Hiroshi MAKINO Yasunobu NAKASE Hiroaki SUZUKI Koichiro MASHIKO Tadashi SUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4  pp. 530-537
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
additioncarry look-ahead adderbinary look-ahead addercarry selectmodified carry selectCMOSVLSI
 Summary | Full Text:PDF(642.3KB)

3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer
Kimio UEDA Nagisa SASAKI Hisayasu SATO Shunji KUBO Koichiro MASHIKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 866-872
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
multiplexerdemultiplexersilicon-bipolarlow-powerECL
 Summary | Full Text:PDF(689.9KB)

A New Emitter-Follower Circuit for High-Speed and Low-Power ECL
Nagisa SASAKI Hisayasu SATO Kimio UEDA Koichiro MASHIKO Hiroshi SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4  pp. 374-380
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Digital Circuits
Keyword: 
ECLemitter-follower circuitbipolarhigh-speed and low-power
 Summary | Full Text:PDF(545.3KB)