Koichiro ISHIBASHI


83nJ/bit Transmitter Using Code-Modulated Synchronized-OOK on 65nm SOTB for Normally-Off Wireless Sensor Networks
Van-Trung NGUYEN Ryo ISHIKAWA Koichiro ISHIBASHI 
Publication:   
Publication Date: 2018/07/01
Vol. E101-C  No. 7  pp. 472-479
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
wireless sensor networksCode Modulationsynchronous-OOKSOTB
 Summary | Full Text:PDF(2.1MB)

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode
Koichiro ISHIBASHI Nobuyuki SUGII Shiro KAMOHARA Kimiyoshi USAMI Hideharu AMANO Kazutoshi KOBAYASHI Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 536-543
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
microprocessorlow power design
 Summary | Full Text:PDF(2.2MB)

On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems
Jinmyoung KIM Toru NAKURA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 560-567
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
DVSfast voltage hoppingresonant supply noisedecoupling capacitornoise reductioncapacitance boosting
 Summary | Full Text:PDF(2.3MB)

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 643-650
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
resonant supply noiseswitched parasitic capacitorssleep blockpower gating
 Summary | Full Text:PDF(2.3MB)

On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 511-519
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
power supply noiseresonanceparasitic capacitancesleep blockDVSpower gating
 Summary | Full Text:PDF(1.7MB)

Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias
Yoshihide KOMATSU Koichiro ISHIBASHI Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 692-698
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
substrate noiserandom variabilityforward body biasself adjustedimpuritieslatch-upCMOSSoC
 Summary | Full Text:PDF(2.2MB)

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond
Koichiro ISHIBASHI Tetsuya FUJIMOTO Takahiro YAMASHITA Hiroyuki OKADA Yukio ARIMA Yasuyuki HASHIMOTO Kohji SAKATA Isao MINEMATSU Yasuo ITOH Haruki TODA Motoi ICHIHASHI Yoshihide KOMATSU Masato HAGIWARA Toshiro TSUKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 250-262
Type of Manuscript:  INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: 
Keyword: 
low powerCMOSSoC90 nmlow voltagevariability
 Summary | Full Text:PDF(2.1MB)

Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond
Yoshihide KOMATSU Yukio ARIMA Koichiro ISHIBASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 384-391
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Soft Error
Keyword: 
cosmic-raycritical chargeforward body biasalpha-particlessoft error rate
 Summary | Full Text:PDF(1.3MB)

FOREWORD
Koichiro ISHIBASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 467-467
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(41.7KB)

CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip
Shoji SHUKURI Kazumasa YANAGISAWA Koichiro ISHIBASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6  pp. 734-739
Type of Manuscript:  Special Section PAPER (Special Issue on Nonvolatile Memories)
Category: Flash Memories
Keyword: 
ie-FlashEPROMfuse and redundancy
 Summary | Full Text:PDF(1005.6KB)

A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
Kenichi OSADA Hisayuki HIGUCHI Koichiro ISHIBASHI Naotaka HASHIMOTO Kenji SHIOZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/01/25
Vol. E83-C  No. 1  pp. 109-114
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
cacheSRAMlow powertwo-portmicroprocessor
 Summary | Full Text:PDF(1.4MB)

Analog Circuit Design Methodology in a Low Power RISC Microprocessor
Koichiro ISHIBASHI Hisayuki HIGUCHI Toshinobu SHIMBO Kunio UCHIYAMA Kenji SHIOZAWA Naotaka HASHIMOTO Shuji IKEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/02/25
Vol. E81-A  No. 2  pp. 210-217
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
Category: 
Keyword: 
microprocessorTLBCAM0. 35 µmCMOS
 Summary | Full Text:PDF(882.4KB)

A 6.93-µm2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
Masataka MINAMI Nagatoshi OHKI Hiroshi ISHIDA Toshiaki YAMANAKA Akihiro SHIMIZU Koichiro ISHIBASHI Akira SATOH Tokuo KURE Takashi NISHIDA Takahiro NAGANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 590-596
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAMfull CMOS celllocal interconnectTiN
 Summary | Full Text:PDF(635.1KB)

An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors
Yasuhisa SHIMAZAKI Katsuhiro NORISUE Koichiro ISHIBASHI Hideo MAEJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12  pp. 1693-1698
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
RISC microprocessorcache memorylow power
 Summary | Full Text:PDF(651.5KB)

High-Speed CMOS SRAM Technologies for Cache Applications
Koichiro ISHIBASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 724-734
Type of Manuscript:  INVITED PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
CMOS SRAMcachewave-pipelinedsense amplifierlow-voltage
 Summary | Full Text:PDF(1017.9KB)

A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers
Koichiro ISHIBASHI Koichi TAKASUGI Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Toshiaki YAMANAKA Akira FUKAMI Naotaka HASHIMOTO Nagatoshi OHKI Akihiro SHIMIZU Takashi HASHIMOTO Takahiro NAGANO Takashi NISHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/06/25
Vol. E78-C  No. 6  pp. 728-734
Type of Manuscript:  Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
Category: 
Keyword: 
 Summary | Full Text:PDF(646.7KB)

A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers
Koichiro ISHIBASHI Kunihiro KOMIYAJI Sadayuki MORITA Toshiro AOTO Shuji IKEDA Kyoichiro ASAYAMA Atsuyosi KOIKE Toshiaki YAMANAKA Naotaka HASHIMOTO Haruhito IIDA Fumio KOJIMA Koichi MOTOHASHI Katsuro SASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 741-748
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
 Summary | Full Text:PDF(683.1KB)

A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's
Koichiro ISHIBASHI Katsuro SASAKI Toshiaki YAMANAKA Hiroshi TOYOSHIMA Fumio KOJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 572-575
Type of Manuscript:  Special Section LETTER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
 Summary | Full Text:PDF(388.8KB)