Koichi TACHIKAKE


A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition
Nozomu TOGAWA Koichi TACHIKAKE Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1340-1349
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
Keyword: 
processor synthesisinstruction set synthesispacked SIMD-type functional unitpacked SIMD-type instructionhardware/software cosynthesis
 Summary | Full Text:PDF(810.6KB)

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions
Nozomu TOGAWA Koichi TACHIKAKE Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3218-3224
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Methodology
Keyword: 
processor synthesispacked SIMD type instructionhardware/software partitioninghardware/software cosynthesisDSP processor
 Summary | Full Text:PDF(409.2KB)