IEICE SEARCH SYSTEM

Kiyohiro FURUTANI

Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories Kiyohiro FURUTANI Takeshi HAMAMOTO Takeo MIKI Masaya NAKANO Takashi KONO Shigeru KIKUDA Yasuhiro KONISHI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/02/01 Vol. E88-C No. 2 pp. 255-263 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: DRAM, redundancy, high speed, high density,
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A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs Kiyohiro FURUTANI Tsukasa OOISHI Mikio ASAKURA Hideto HIDAKA Hideyuki OZAKI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/20 Vol. E80-C No. 4 pp. 582-589 Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Keyword: DRAM, test, redundancy,
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A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories Tsukasa OOISHI Yuichiro KOMIYA Kei HAMADE Mikio ASAKURA Kenichi YASUDA Kiyohiro FURUTANI Tetsuo KATO Hideto HIDAKA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/20 Vol. E79-C No. 7 pp. 986-996 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
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Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs Tadaaki YAMAUCHI Koji TANAKA Kiyohiro FURUTANI Yoshikazu MOROOKA Hiroshi MIYAMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/20 Vol. E78-C No. 7 pp. 858-865 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: self-timing data-bus, timing delay, device fluctuation, amplifier, 64-Mb DRAMs,
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An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's Tsukasa OOISHI Yuichiro KOMIYA Kei HAMADE Mikio ASAKURA Kenichi YASUDA Kiyohiro FURUTANI Hideto HIDAKA Hiroshi MIYAMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/06/20 Vol. E78-C No. 6 pp. 719-727 Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995)) Category: Keyword:
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An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's Yasuhiko TSUKIKAWA Takeshi KAJIMOTO Yasuhiko OKASAKA Yoshikazu MOROOKA Kiyohiro FURUTANI Hiroshi MIYAMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/05/20 Vol. E77-C No. 5 pp. 864-868 Type of Manuscript: Special Section LETTER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) Category: Keyword:
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An Intelligent Cache Memory Chip Suitable for Logical Inference Kenichi YASUDA Kiyohiro FURUTANI Atsushi MAEDA Shoichi WAKANO Hiroshi NAKASHIMA Yasutaka TAKEDA Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/11/20 Vol. E74-C No. 11 pp. 3796-3802 Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor) Category: System VLSI Keyword:
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