Kimihiro YAMAKOSHI


Experimental 5-Tb/s Packet-by-Packet Wavelength Switching System Using 2.5 -Gb/s 8-λ WDM Links
Kimihiro YAMAKOSHI Nobuaki MATSUURA Kohei NAKAI Eiji OKI Naoaki YAMANAKA Takaharu OHYAMA Yuji AKAHORI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2002/07/01
Vol. E85-B  No. 7  pp. 1293-1301
Type of Manuscript:  PAPER
Category: Switching
Keyword: 
packetswitchWDMAWG
 Summary | Full Text:PDF(2.1MB)

A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz
Hiroki SUTOH Kimihiro YAMAKOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C  No. 7  pp. 1334-1340
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLLCMOS/SIMOXVCOclockjitterskewlock range
 Summary | Full Text:PDF(2MB)

A New Routing Method Considering Neighboring-Wire Capacitance Constraints
Takumi WATANABE Kimihiro YAMAKOSHI Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2679-2687
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
routingwire capacitancedeep-submicron designCADVLSI
 Summary | Full Text:PDF(839.1KB)

A 40-Gb/s 88 ATM Switch LSI Using 0. 25-µmCMOS/SIMOX
Yusuke OHTOMO Sadayuki YASUDA Masafumi NOGAWA Jun-ichi INOUE Kimihiro YAMAKOSHI Hirotoshi SAWADA Masayuki INO Shigeki HINO Yasuhiro SATO Yuichiro TAKEI Takumi WATANABE Ken TAKEYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 737-745
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: Network
Keyword: 
SOICMOSATMhigh-speed
 Summary | Full Text:PDF(986.3KB)

An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology
Takumi WATANABE Yusuke OHTOMO Kimihiro YAMAKOSHI Yuichiro TAKEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/04/25
Vol. E81-A  No. 4  pp. 677-684
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
routing methodologymaze routerlayoutCADVLSI
 Summary | Full Text:PDF(835KB)

A Clock Distribution Technique with an Automatic Skew Compensation Circuit
Hiroki SUTOH Kimihiro YAMAKOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/02/25
Vol. E81-C  No. 2  pp. 277-283
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock skewclock distributioncompensationvariable delay lineCMOS
 Summary | Full Text:PDF(589.2KB)