Kewal K. SALUJA


Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment
Yoshinobu HIGAMI Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/06/01
Vol. E96-D  No. 6  pp. 1323-1331
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generationfault simulationclock linedelay fault
 Summary | Full Text:PDF(595KB)

A Study of Capture-Safe Test Generation Flow for At-Speed Testing
Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA Yuta YAMATO Atsushi TAKASHIMA Hiroshi FURUKAWA Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7  pp. 1309-1318
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
at-speed scan testingtest generationX-bit identificationX-fillingcapture-safety checking
 Summary | Full Text:PDF(3.5MB)

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3128-3135
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
test generationtransistor defectsstuck-at testsdefect coverage
 Summary | Full Text:PDF(299.6KB)

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3506-3513
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
fault simulationtest generationstuck-open faultsstuck-at testsdefect coverage
 Summary | Full Text:PDF(283.9KB)

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 690-699
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Defect-Based Testing
Keyword: 
transistor shortfault simulationtest generationstuck-at test tool
 Summary | Full Text:PDF(346.3KB)

A Novel ATPG Method for Capture Power Reduction during Scan Testing
Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Tatsuya SUZUKI Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/09/01
Vol. E90-D  No. 9  pp. 1398-1405
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
scan testingcapture powerX-bitIR-drop
 Summary | Full Text:PDF(1.6MB)

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability
Masato NAKAZATO Satoshi OHTAKE Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 296-305
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
sequential circuittest generationsynthesis for testabilityfinite state machinetest knowledge
 Summary | Full Text:PDF(641.6KB)

A Per-Test Fault Diagnosis Method Based on the X-Fault Model
Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Yuta YAMATO Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/11/01
Vol. E89-D  No. 11  pp. 2756-2765
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
fault diagnosisper-testX-fault model
 Summary | Full Text:PDF(829.4KB)

A New Method for Low-Capture-Power Test Generation for Scan Testing
Xiaoqing WEN Yoshiyuki YAMASHITA Seiji KAJIHARA Laung-Terng WANG Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/05/01
Vol. E89-D  No. 5  pp. 1679-1686
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
scan testingcapture powerX-bitIR-drop
 Summary | Full Text:PDF(814.9KB)

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch
Yoshiyuki NAKAMURA Thomas CLOUQUEUR Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3  pp. 1165-1172
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault diagnosiserror identificationat-speed testlow speed tester
 Summary | Full Text:PDF(462.4KB)

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies
Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/04/01
Vol. E88-D  No. 4  pp. 703-710
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
fault diagnosisIDDQtransistor leakage fault modelmultiple power supplycircuit partitioning
 Summary | Full Text:PDF(487.3KB)

An Alternative Test Generation for Path Delay Faults by Using Ni-Detection Test Sets
Hiroshi TAKAHASHI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2650-2658
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
test generationpath delay faults N-propagation test-pair setcombinational circuits
 Summary | Full Text:PDF(587.1KB)

Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation
Hiroshi TAKAHASHI Marong PHADOONGSIDHI Yoshinobu HIGAMI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1515-1525
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
diagnosiscrosstalk faultfault simulationsequential circuit
 Summary | Full Text:PDF(870.8KB)

Transistor Leakage Fault Diagnosis for CMOS Circuits
Xiaoqing WEN Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 697-705
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
fault diagnosistransistor leakage faultIDDQprimary outputfault simulationdiagnostic test generation
 Summary | Full Text:PDF(868.3KB)

Transistor Leakage Fault Diagnosis with IDDQ and Logic Information
Wen XIAOQING Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/04/25
Vol. E81-D  No. 4  pp. 372-381
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault diagnosistransistor leakage faultIDDQ testingfault simulationdiagnostic vector generation
 Summary | Full Text:PDF(985.7KB)

Theory and Techniques for Testing Check Bits of RAMs with On-Chip ECC
Manoj FRANKLIN Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/10/25
Vol. E76-D  No. 10  pp. 1243-1252
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
error-correcting codeson-chip ECCpattern sensitive faultsRAM testingtest algorithms
 Summary | Full Text:PDF(859.9KB)