Kentaroh KATOH


Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/03/01
Vol. E92-D  No. 3  pp. 433-442
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
dual circuitsmaster and slave scan pathsdelay fault testingconcurrent error detectionDFT
 Summary | Full Text:PDF(931.4KB)

Design for Delay Fault Testability of 2-Rail Logic Circuits
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2  pp. 336-341
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
2-rail logic circuitsdesign for testabilitydelay fault testingscan designset-reset operation
 Summary | Full Text:PDF(455.8KB)