Kensuke SHIMIZU


Dynamic Range Compression Characteristics Using an Interpolating Polynomial for Digital Audio Systems
Shugang WEI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/02/01
Vol. E88-A  No. 2  pp. 586-589
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
dynamic range controlcompression characteristicinterpolating polynomialdigital audio systemgain
 Summary | Full Text:PDF(118.1KB)

New Three-Level Boolean Expression Based on EXOR Gates
Ryoji ISHIKAWA Takashi HIRAYAMA Goro KODA Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/05/01
Vol. E87-D  No. 5  pp. 1214-1222
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
EXOR gatesthree-level logicpseudoproductcompact designtestability
 Summary | Full Text:PDF(655.1KB)

Detection of Autosymmetry in Logic Functions Using Spectrum Technique
Ryoji ISHIKAWA Goro KODA Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2691-2697
Type of Manuscript:  PAPER
Category: Computer System Element
Keyword: 
spectrum techniqueautosymmetryEXOR-based representationsthree-level logic
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A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number Representation
Shugang WEI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/12/25
Vol. E83-D  No. 12  pp. 2056-2064
Type of Manuscript:  PAPER
Category: Theory/Models of Computation
Keyword: 
symmetric residue number systemsigned-digit(SD) number representationSD adderbinary modulo m adder treemodulo m multiplication
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Compact Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits
Shugang WEI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1647-1654
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Non-Binary Architectures
Keyword: 
residue number systemsigned-digit (SD) number representationend-around SD adderbinary adder treemultiple-valued circuits
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Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions
Takashi HIRAYAMA Goro KODA Yasuaki NISHITANI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/09/25
Vol. E82-D  No. 9  pp. 1278-1286
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
logic synthesisexclusive-orsingle stuck-at faulteasily testable realization
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Minimization of AND-EXOR Expressions for Symmetric Functions
Takashi HIRAYAMA Yasuaki NISHITANI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 567-570
Type of Manuscript:  Special Section LETTER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
logic synthesisAND-EXOR expressionsymmetric functionlogic minimization algorithm
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Modulo 2p-1 Arithmetic Hardware Algorithm Using Signed-Digit Number Representation
Shugang WEI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/03/25
Vol. E79-D  No. 3  pp. 242-246
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
residue number systemredundant modular representationsigned-digit number representationMersenne numberbinary adder tree
 Summary | Full Text:PDF(276.2KB)

Lower Bounds on Size of Periodic Functions in Exclusive-OR Sum-of-Products Expressions
Yasuaki NISHITANI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3  pp. 475-482
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Category: Computer Aided Design (CAD)
Keyword: 
exclusive-OR sum-of-productssize of circuitslower boundlogic minimizationlogic design
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Multilevel Network Design for Parity Functions with MOS Cells under Limitations on the Number of Series Transistors
Yasuaki NISHITANI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/08/25
Vol. E71-E  No. 8  pp. 791-798
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
 Summary | Full Text:PDF(564.1KB)

Synthesis of Multilevel Feed-Forward NAND Networks
Kensuke SHIMIZU Shugang WEI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1986/07/25
Vol. E69-E  No. 7  pp. 785-787
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
 Summary | Full Text:PDF(189.3KB)