Ken TAKEUCHI

Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor
Kousuke MIYAJI  Kentaro HONDA  Shuhei TANAKAMARU  Shinji MIYANO  Ken TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 564-571
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
6T/8T-SRAM,  asymmetric pass gate transistor,  local electron injection,  disturb/write margin,  read speed, 
  Summary |  Full Text:PDF (4.5MB)
Initialize and Weak-Program Erasing Scheme for High-Performance and High-Reliability Ferroelectric NAND Flash Solid-State Drive
Kousuke MIYAJI  Ryoji YAJIMA  Teruyoshi HATANAKA  Mitsue TAKAHASHI  Shigeki SAKAI  Ken TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 609-616
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
ferroelectric FET,  NAND flash memory,  solid-state drive,  bit-by-bit verifying technique,  history effect, 
  Summary |  Full Text:PDF (1.8MB)
Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell VTH Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs)
Teruyoshi HATANAKA  Mitsue TAKAHASHI  Shigeki SAKAI  Ken TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 539-547
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
NAND flash memory,  ferroelectric,  solid-state drive,  SSD, 
  Summary |  Full Text:PDF (1.4MB)
Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories
Tadashi YASUFUKU  Koichi ISHIDA  Shinji MIYAMOTO  Hiroto NAKAI  Makoto TAKAMIYA  Takayasu SAKURAI  Ken TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 317-323
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
SSD,  boost converter,  charge pump,  inductor design,  TSV's, 
  Summary |  Full Text:PDF (1.3MB)
A Double-Leve1-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories
Ken TAKEUCHI  Tomoharu TANAKA  Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/20
Vol. E79-C  No. 7  pp. 1013-1020
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory
Keyword: 
  Summary |  Full Text:PDF (639.1KB)