Keikichi TAMARU


Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
Kazutoshi KOBAYASHI Masanao YAMAOKA Yukifumi KOBAYASHI Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2400-2408
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
VLSIfunctional memoryDRAMparallel processorblock matching
 Summary | Full Text:PDF(868.6KB)

Layout Dependent Matching Analysis of CMOS Circuits
Kenichi OKADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2  pp. 348-355
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
CMOSmatchingmicro-loading-effectfluctuation
 Summary | Full Text:PDF(168.8KB)

A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization
Kazutoshi KOBAYASHI Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2  pp. 215-222
Type of Manuscript:  Special Section PAPER (Special Section on VLSI for Digital Signal Processing)
Category: 
Keyword: 
vector quantizationfunctional memoryparallel processorlow-rate image compressionnoise robustnessMSHVQ
 Summary | Full Text:PDF(665.6KB)

A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
Masanori HASHIMOTO Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/01/25
Vol. E82-A  No. 1  pp. 159-166
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
input reorderingtransistor reorderingpower estimation
 Summary | Full Text:PDF(317.8KB)

CAM-Based Array Converter for URR Floating-Point Arithmetic
Kuei-Ming LU Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/10/25
Vol. E81-D  No. 10  pp. 1120-1130
Type of Manuscript:  PAPER
Category: Computer Applications
Keyword: 
floating-point arithmeticcontent addressable memoryiterative arrayURR format conversion
 Summary | Full Text:PDF(839KB)

An LSI for Low Bit-Rate Image Compression Using Vector Quantization
Kazutoshi KOBAYASHI Noritsugu NAKAMURA Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 718-724
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
parallel processormemory-basedvector quantizationlow bit-rate image compressionlow powerSIMD
 Summary | Full Text:PDF(748.2KB)

Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load
Akio HIRATA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/03/25
Vol. E81-A  No. 3  pp. 462-469
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
short-circuit power dissipationshort-circuit currentresistive-capacitive loadCRC π loadoutput waveformgate delay
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A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ
Kazutoshi KOBAYASHI Masayoshi KINOSHITA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 970-975
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multi Processors
Keyword: 
parallel processormemory-basevector quantizationlow bit-rate image compressionSIMD
 Summary | Full Text:PDF(632KB)

A Current Mode Cyclic A/D Converter with Submicron Processes
Masaki KONDO Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/02/25
Vol. E80-A  No. 2  pp. 360-364
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
Category: 
Keyword: 
A/DA/D convertercurrent moderatio-independentRGC
 Summary | Full Text:PDF(341.3KB)

A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs
Vasily G. MOSHNYAGA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1389-1395
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
Keyword: 
high-level synthesisASIC design methodology
 Summary | Full Text:PDF(605.3KB)

Estimation of short-Circuit Power Dissipation for Static CMOS Gates
Akio HIRATA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 304-311
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
short-circuit power dissipationshort-circit currentsimulation of power dissipationlow power disignpower estimation
 Summary | Full Text:PDF(566.4KB)

Model-Adaptable Parameter Extraction System for MOSFET Models
Masaki KONDO Takashi MORIE Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/05/25
Vol. E78-A  No. 5  pp. 569-572
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Fall Conference)
Category: 
Keyword: 
parameter extraction systeminitial value estimationMOSFET characterization
 Summary | Full Text:PDF(272.1KB)

Register-Transfer Module Selection for Sub-Micron ASIC Design
Vasily G. MOSHNYAGA Yutaka MORI Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3  pp. 252-255
Type of Manuscript:  Special Section LETTER (Special Issue on Synthesis and Verification of Hardware Design)
Category: 
Keyword: 
module selectionregister-transfer synthesis
 Summary | Full Text:PDF(358.9KB)

Development of Module Generators from Extracted Design Procedures--Application to Analog Device Generation--
Takashi MORIE  Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/02/25
Vol. E78-A  No. 2  pp. 160-168
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Computer Aided Design)
Category: 
Keyword: 
device layoutmodule generationanalog LSIstore and re-usedesign procedure
 Summary | Full Text:PDF(888.4KB)

Experiments with Power Optimization in Gate Sizing
Guangqiu CHEN Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11  pp. 1913-1916
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category: 
Keyword: 
low power designpower dissipationgate sizingarea–power–delay tradeoff
 Summary | Full Text:PDF(267.1KB)

The Trend of Functional Memory Development
Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11  pp. 1545-1554
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
memoryfunctional memorycontent addressable memoryassociative memoryprocessor array
 Summary | Full Text:PDF(871.6KB)

Design of a Multiplier-Accumulator for High Speed lmage Filtering
Farhad Fuad ISLAM Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/11/25
Vol. E76-A  No. 11  pp. 2022-2032
Type of Manuscript:  PAPER
Category: VLSI Design Technology
Keyword: 
binary multiplier-accumulatorthroughputimage filteringVLSI architecture
 Summary | Full Text:PDF(843.3KB)

A Language for Designing Module Generators
Vasily G. MOSHNYAGA Keikichi TAMARU Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9  pp. 1066-1074
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Hardware Design Languages
Keyword: 
module generatorhardware disign language
 Summary | Full Text:PDF(722.8KB)

An Architecture for High Speed Array Multiplier
Farhad Fuad ISLAM Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/08/25
Vol. E76-A  No. 8  pp. 1326-1333
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
binary multiplicationarray multiplerVLSI architecture
 Summary | Full Text:PDF(656.7KB)

Hardware Architecture for Kohonen Network
Hidetoshi ONODERA Kiyoshi TAKESHITA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1159-1166
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
Keyword: 
neural networkKohonen networkmassively parallel computationcontent addressable memory
 Summary | Full Text:PDF(712.9KB)

A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture
Kazutoshi KOBAYASHI Keikichi TAMARU Hiroto YASUURA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1151-1158
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Memory-Based Parallel Processor Architectures
Keyword: 
parallel processormemory-based simple structurelogical and arithmetic operations
 Summary | Full Text:PDF(734.9KB)

FOREWORD
Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11  pp. 1303-1303
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(84.5KB)

Extraction of Behavioral Descriptions from Synchronous Sequential Circuits
Masahiko OHMURA Hiroto YASUURA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1239-1246
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
behavioral extractionlogic verification
 Summary | Full Text:PDF(580KB)

An Architecture for FFT Butterfly Computation with Merged Core Multiplication technique
Farhad Fuad ISLAM Hiroto YASUURA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1810-1812
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Signals, Circuits and Images
Keyword: 
 Summary | Full Text:PDF(180.2KB)

Module Generation of a CMOS Op Amp Using a Non-linear Optimization Method
Hidetoshi ONODERA Hiroyuki KANBARA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/10/25
Vol. E71-E  No. 10  pp. 947-949
Type of Manuscript:  Special Section LETTER (Special Issue: Papers from 1988 Autumn Convention IEICE)
Category: Integrated Circuit
Keyword: 
 Summary | Full Text:PDF(203.6KB)