Kazuyoshi TAKAGI


Algorithms for Evaluating the Matrix Polynomial I+A+A2+…+AN-1 with Reduced Number of Matrix Multiplications
Kotaro MATSUMOTO Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   
Publication Date: 2018/02/01
Vol. E101-A  No. 2  pp. 467-471
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
evaluation of matrix polynomialmatrix multiplication
 Summary | Full Text:PDF(565.7KB)

High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation
Masamitsu TANAKA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 703-709
Type of Manuscript:  Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
Category: 
Keyword: 
digital arithmeticdigit-serial processinghardware algorithmrapid single-flux-quantum logicsigned-digit representationsystolic array
 Summary | Full Text:PDF(471.1KB)

RSFQ 4-bit Bit-Slice Integer Multiplier
Guang-Ming TANG Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 697-702
Type of Manuscript:  Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
Category: 
Keyword: 
multipliersingle-flux-quantum (SFQ)microprocessorsuperconducting integrated circuits
 Summary | Full Text:PDF(2MB)

A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model
Takahiro KAWAGUCHI Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2556-2564
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
single-flux-quantum circuitstatic timing analysisformal verification
 Summary | Full Text:PDF(1.1MB)

Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis
Akihiro SUDA Hideki TAKASE Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2498-2506
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesisarray partitioningbuffer managementPolyhedral Optimization
 Summary | Full Text:PDF(1.2MB)

Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors
Akira FUJIMAKI Masamitsu TANAKA Ryo KASAGI Katsumi TAKAGI Masakazu OKADA Yuhi HAYAKAWA Kensuke TAKATA Hiroyuki AKAIKE Nobuyuki YOSHIKAWA Shuichi NAGASAWA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 157-165
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
advanced processcell-based design techniquehigh-end computinglarge-scale integrationrapid single-flux-quantum circuits
 Summary | Full Text:PDF(2.3MB)

Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process
Xizhu PENG Yuki YAMANASHI Nobuyuki YOSHIKAWA Akira FUJIMAKI Naofumi TAKAGI Kazuyoshi TAKAGI Mutsuo HIDAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 188-193
Type of Manuscript:  Special Section PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
floating point unitmultiplierLSRDPSFQ circuitsuperconductive integrated circuit
 Summary | Full Text:PDF(2.2MB)

Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation
Shuichi NAGASAWA Kenji HINODE Tetsuro SATOH Mutsuo HIDAKA Hiroyuki AKAIKE Akira FUJIMAKI Nobuyuki YOSHIKAWA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 132-140
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
superconducting fabrication technologyNb/AlOx/Nb Josephson junctionsingle flux quantumplanarizationshift register
 Summary | Full Text:PDF(5.3MB)

Circuit Description and Design Flow of Superconducting SFQ Logic Circuits
Kazuyoshi TAKAGI Nobutaka KITO Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 149-156
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
single-flux-quantum circuitdesign methodologycircuit descriptionlogic designlayout designdesign verification
 Summary | Full Text:PDF(2.8MB)

A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition
Kazuhiro NAKAMURA Ryo SHIMAZAKI Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 456-467
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
speech recognitionhidden Markov model (HMM)VLSI architectureisolated word recognition
 Summary | Full Text:PDF(2.3MB)

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits
Kazuyoshi TAKAGI Yuki ITO Shota TAKESHIMA Masamitsu TANAKA Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3  pp. 288-295
Type of Manuscript:  Special Section PAPER (Special Section on Superconducting Signal Processing Technologies)
Category: 
Keyword: 
single-flux-quantum circuitdesign methodologyclock tree synthesisclock skew
 Summary | Full Text:PDF(1.1MB)

Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm
Masamitsu TANAKA Koji OBATA Yuki ITO Shota TAKESHIMA Motoki SATO Kazuyoshi TAKAGI Naofumi TAKAGI Hiroyuki AKAIKE Akira FUJIMAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/04/01
Vol. E93-C  No. 4  pp. 435-439
Type of Manuscript:  Special Section PAPER (Special Section on Frontiers of Superconductive Electronics)
Category: Digital Applications
Keyword: 
single-flux-quantum circuitcomputer-aided designwire routerpassive transmission line
 Summary | Full Text:PDF(970.9KB)

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing
Kazuhiro NAKAMURA Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/02/01
Vol. E93-D  No. 2  pp. 300-305
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
speech recognitionhidden Markov model (HMM)VLSI architecture
 Summary | Full Text:PDF(549KB)

A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits
Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3772-3782
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock schedulingclock skewmicropipelineRSFQ
 Summary | Full Text:PDF(460.1KB)

A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits
Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/12/01
Vol. E90-C  No. 12  pp. 2278-2284
Type of Manuscript:  PAPER
Category: Superconducting Electronics
Keyword: 
sequential circuit synthesisone-hot encodingsingle-flux-quantum (SFQ)
 Summary | Full Text:PDF(255.3KB)

Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams
Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1  pp. 257-266
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
logic synthesisdual-railRSFQbinary decision diagrams (BDDs)
 Summary | Full Text:PDF(462.9KB)

A Hardware Algorithm for Integer Division Using the SD2 Representation
Naofumi TAKAGI Shunsuke KADOWAKI Kazuyoshi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/10/01
Vol. E89-A  No. 10  pp. 2874-2881
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
computer arithmeticdivisioninteger divisionhardware algorithmsigned-digit representationVLSI
 Summary | Full Text:PDF(377.5KB)

Digit-Recurrence Algorithm for Computing Reciprocal Square-Root
Naofumi TAKAGI Daisuke MATSUOKA Kazuyoshi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/01/01
Vol. E86-A  No. 1  pp. 221-228
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
computer arithmeticreciprocal square-roothardware algorithmdigit-recurrencecomputer graphics
 Summary | Full Text:PDF(229.7KB)

A VLSI Algorithm for Division in GF(2m) Based on Extended Binary GCD Algorithm
Yasuaki WATANABE Naofumi TAKAGI Kazuyoshi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/05/01
Vol. E85-A  No. 5  pp. 994-999
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
finite field arithmeticdivision in finite fieldhardware algorithmVLSI algorithm
 Summary | Full Text:PDF(234.2KB)

Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization
Kazuyoshi TAKAGI Hiroshi HATAKEDA Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2407-2413
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Free BDDPass-Transistor LogicBoolean functionlogic minimization
 Summary | Full Text:PDF(680.1KB)

Hardware Synthesis from C Programs with Estimation of Bit Length of Variables
Osamu OGAWA Kazuyoshi TAKAGI Yasufumi ITOH Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2338-2346
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesishardware/software codesignVHDLC languagecompiler
 Summary | Full Text:PDF(724.5KB)

Minimum Cut Linear Arrangement of p-q Dags for VLSI Layout of Adder Trees
Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/05/25
Vol. E82-A  No. 5  pp. 767-774
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graph algorithmminimum cut linear arrangementVLSI layoutadder treemultiplier
 Summary | Full Text:PDF(690KB)

Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
Kazuhiro NAKAMURA Shinji KIMURA Kazuyoshi TAKAGI Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2515-2520
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
Keyword: 
timing verificationmaximum delay analysismultiple clock operationfalse path
 Summary | Full Text:PDF(546.5KB)

Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses
Kazuyoshi TAKAGI Koyo NITTA Hironori BOUNO Yasuhiko TAKENAGA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/04/25
Vol. E80-A  No. 4  pp. 663-669
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
computational complexityBoolean functionordered binary decision diagramsatisfiabilitycombinational circuitcutwidthsum-of-product formzero-suppressed binary decision diagrams (BDD)ternary decision diagram
 Summary | Full Text:PDF(675.4KB)