Kazuya HISAMITSU

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential
Dondee NAVARRO  Takeshi MIZOGUCHI  Masami SUETAKE  Kazuya HISAMITSU  Hiroaki UENO  Mitiko MIURA-MATTAUSCH  Hans Jurgen MATTAUSCH  Shigetaka KUMASHIRO  Tetsuya YAMAGUCHI  Kyoji YAMASHITA  Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5  pp. 1079-1086
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
pinch-off region,  channel-length modulation,  overlap capacitance,  surface-potential-based modeling,  circuit simulation, 
  Summary |  Full Text:PDF (1MB)
Circuit-Simulation Model of Cgd Changes in Small-Size MOSFETs Due to High Channel-Field Gradients
Dondee NAVARRO  Hiroaki KAWANO  Kazuya HISAMITSU  Takatoshi YAMAOKA  Masayasu TANAKA  Hiroaki UENO  Mitiko MIURA-MATTAUSCH  Hans Jurgen MATTAUSCH  Shigetaka KUMASHIRO  Tetsuya YAMAGUCHI  Kyoji YAMASHITA  Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/03/01
Vol. E86-C  No. 3  pp. 474-480
Type of Manuscript: INVITED PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
Category: 
Keyword: 
gate-drain capacitance,  surface-potential based modeling,  lateral field gradient,  pocket-implant technology, 
  Summary |  Full Text:PDF (1MB)