Kazutoshi KOBAYASHI


Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model
Takuya KOMAWAKI Michitarou YABUUCHI Ryo KISHIDA Jun FURUTA Takashi MATSUMOTO Kazutoshi KOBAYASHI 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2758-2763
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Random Telegraph NoisereliabilityVerilog-AMS
 Summary | Full Text:PDF(2.1MB)

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode
Koichiro ISHIBASHI Nobuyuki SUGII Shiro KAMOHARA Kimiyoshi USAMI Hideharu AMANO Kazutoshi KOBAYASHI Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 536-543
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
microprocessorlow power design
 Summary | Full Text:PDF(2.2MB)

Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets
Jun FURUTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C  No. 4  pp. 298-303
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
Neutron-induced Soft ErrorMultiple Cell Upset (MCU)cell distancewell-contact densityFlip-Flop
 Summary | Full Text:PDF(796.1KB)

Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs
Michitarou YABUUCHI Ryo KISHIDA Kazutoshi KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2367-2372
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
BTIprocess variationreliability
 Summary | Full Text:PDF(1.2MB)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing
Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Hajime SHIMADA Kazutoshi KOBAYASHI Hiroyuki KANBARA Hiroyuki OCHI Takashi IMAGAWA Kazutoshi WAKABAYASHI Masanori HASHIMOTO Takao ONOYE Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2518-2529
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
reconfigurable architecturesoft errorradiation testbehavioral synthesisstate machine
 Summary | Full Text:PDF(3.8MB)

FOREWORD
Kazutoshi KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/07/01
Vol. E97-A  No. 7  pp. 1443-1443
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(195.7KB)

A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect
Kuiyuan ZHANG Jun FURUTA Ryosuke YAMAMOTO Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 511-517
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
DMRsoft errorMCUdevice simulation
 Summary | Full Text:PDF(2MB)

Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures
Chikara HAMANAKA Ryosuke YAMAMOTO Jun FURUTA Kanto KUBOTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2669-2675
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
soft errorhardened designvariabilitytest structureshift register
 Summary | Full Text:PDF(3.1MB)

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
Jun FURUTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 340-346
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
TMRbuilt-in soft errorSEUSET
 Summary | Full Text:PDF(385.2KB)

A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations
Kazutoshi KOBAYASHI Kazuya KATSUKI Manabu KOTANI Yuuri SUGIHARA Yohei KUME Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1919-1926
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Low-Power and High-Performance VLSI Circuit Technology
Keyword: 
variation-awarereconfigurable deviceFPGAyieldDFM
 Summary | Full Text:PDF(689.6KB)

A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations
Kazuya KATSUKI Manabu KOTANI Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 699-707
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
within-die variationreconfigurable deviceFPGALUT (look-up table)yield
 Summary | Full Text:PDF(663.5KB)

A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era
Kazutoshi KOBAYASHI Akihiko HIGUCHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6  pp. 838-843
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
sleep transistordecoupling capacitorMTCMOSlow power
 Summary | Full Text:PDF(442KB)

Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect
Yoichi YUYAMA Akira TSUCHIYA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 327-333
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Interface and Interconnect Techniques
Keyword: 
alternate self shieldingon-chip global interconnectcritical transition and bus encoding
 Summary | Full Text:PDF(876.3KB)

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era
Kazutoshi KOBAYASHI Masao ARAMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 552-558
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
parallel processingVLIWSMTlow powernanometerleakage power
 Summary | Full Text:PDF(1.1MB)

Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers
Akihiko HIGUCHI Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/04/01
Vol. E87-A  No. 4  pp. 823-829
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
embedded processorpower estimationinstruction-level
 Summary | Full Text:PDF(1.3MB)

A Comprehensive Simulation and Test Environment for Prototype VLSI Verification
Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 630-636
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Verification
Keyword: 
simulationtestVLSItesterverification
 Summary | Full Text:PDF(1.4MB)

An Efficient Motion Estimation Algorithm Using a Gyro Sensor
Kazutoshi KOBAYASHI Ryuta NAKANISHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3  pp. 530-538
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Video/Image Coding
Keyword: 
motion estimationgyro sensorMPEG-4
 Summary | Full Text:PDF(537.9KB)

A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones
Kazutoshi KOBAYASHI Makoto EGUCHI Takuya IWAHASHI Takehide SHIBAYAMA Xiang LI Kosuke TAKAI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 193-201
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
VLSIDSPMSHVQvideophonevideo compression
 Summary | Full Text:PDF(1001.1KB)

Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
Kazutoshi KOBAYASHI Masanao YAMAOKA Yukifumi KOBAYASHI Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2400-2408
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
VLSIfunctional memoryDRAMparallel processorblock matching
 Summary | Full Text:PDF(868.6KB)

A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization
Kazutoshi KOBAYASHI Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2  pp. 215-222
Type of Manuscript:  Special Section PAPER (Special Section on VLSI for Digital Signal Processing)
Category: 
Keyword: 
vector quantizationfunctional memoryparallel processorlow-rate image compressionnoise robustnessMSHVQ
 Summary | Full Text:PDF(665.6KB)

An LSI for Low Bit-Rate Image Compression Using Vector Quantization
Kazutoshi KOBAYASHI Noritsugu NAKAMURA Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 718-724
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
parallel processormemory-basedvector quantizationlow bit-rate image compressionlow powerSIMD
 Summary | Full Text:PDF(748.2KB)

A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ
Kazutoshi KOBAYASHI Masayoshi KINOSHITA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 970-975
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multi Processors
Keyword: 
parallel processormemory-basevector quantizationlow bit-rate image compressionSIMD
 Summary | Full Text:PDF(632KB)

A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture
Kazutoshi KOBAYASHI Keikichi TAMARU Hiroto YASUURA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1151-1158
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Memory-Based Parallel Processor Architectures
Keyword: 
parallel processormemory-based simple structurelogical and arithmetic operations
 Summary | Full Text:PDF(734.9KB)