Kazuteru NAMBA


Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/10/01
Vol. E97-D  No. 10  pp. 2719-2729
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
small-delay defectsfault coveragesegmented scancontrol pointobservation point
 Summary | Full Text:PDF(752KB)

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/03/01
Vol. E97-D  No. 3  pp. 533-540
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
small-delay defectstest compactiontest application timetest data volumeon-chip delay measurement
 Summary | Full Text:PDF(435.6KB)

Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA
Kazuteru NAMBA Nobuhide TAKASHINA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1613-1623
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Test and Verification
Keyword: 
small delay defectsdelay measurementDVMC (delay value measurement circuit)FPGA (field programmable gate array)global routing resource
 Summary | Full Text:PDF(917KB)

Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/05/01
Vol. E96-D  No. 5  pp. 1219-1222
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
small delay faultstest coverageflip-flopclock pulse
 Summary | Full Text:PDF(240.7KB)

Construction of BILBO FF with Soft-Error-Tolerant Capability
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/05/01
Vol. E94-D  No. 5  pp. 1045-1050
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
soft-error-toleranceDFT (design for test)BISER (built-in soft-error resilience)BILBO (built-in logic block observer)reconfigurable C-element
 Summary | Full Text:PDF(221.8KB)

Single-Event-Upset Tolerant RS Flip-Flop with Small Area
Kazuteru NAMBA Kengo NAKASHIMA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/12/01
Vol. E93-D  No. 12  pp. 3407-3409
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
soft errorsingle-event-upset (SEU) tolerancereset-set flip-flop (RS-FF)interlocking feedback loop
 Summary | Full Text:PDF(240.1KB)

Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9  pp. 2295-2303
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
two-rail logic circuitpath delay faulttestabilityfunctional sensitizabilityover-testing
 Summary | Full Text:PDF(447.9KB)

Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability
Shuangyu RUAN Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/08/01
Vol. E92-D  No. 8  pp. 1534-1541
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
soft errorwide pulseflip-flopC-elementdelay element
 Summary | Full Text:PDF(466.7KB)

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/03/01
Vol. E92-D  No. 3  pp. 433-442
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
dual circuitsmaster and slave scan pathsdelay fault testingconcurrent error detectionDFT
 Summary | Full Text:PDF(931.4KB)

Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2  pp. 269-282
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test compressionstatistical codingrun-length codingdelay fault testingtwo-pattern testingscan testing
 Summary | Full Text:PDF(1.2MB)

Design for Delay Fault Testability of 2-Rail Logic Circuits
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2  pp. 336-341
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
2-rail logic circuitsdesign for testabilitydelay fault testingscan designset-reset operation
 Summary | Full Text:PDF(455.8KB)

Redundant Design for Wallace Multiplier
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/09/01
Vol. E89-D  No. 9  pp. 2512-2524
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
Wallace multiplierbit-slice reconfiguration redundant designdefect-toleranceyield
 Summary | Full Text:PDF(1.6MB)

Proposal of Testable Multi-Context FPGA Architecture
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/05/01
Vol. E89-D  No. 5  pp. 1687-1693
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
multi-context FPGAsingle stuck-at faultdesign for testability
 Summary | Full Text:PDF(412.9KB)

Scan Design for Two-Pattern Test without Extra Latches
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12  pp. 2777-2785
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testingdelay fault testingscan designenhanced scan
 Summary | Full Text:PDF(1.5MB)

Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/09/01
Vol. E88-D  No. 9  pp. 2135-2142
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testingadjacency testdeterministic test generationBIST
 Summary | Full Text:PDF(264.3KB)

Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities
Kazuteru NAMBA Eiji FUJIWARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/06/01
Vol. E85-A  No. 6  pp. 1426-1430
Type of Manuscript:  LETTER
Category: Coding Theory
Keyword: 
unequal error protection codetwo-level UEP codesburst error correcting Fire code
 Summary | Full Text:PDF(864.8KB)