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Kazuteru NAMBA

Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF Wenpo ZHANG Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/05/01 Vol. E96-D No. 5 pp. 1219-1222 Type of Manuscript: LETTER Category: Dependable Computing Keyword: small delay faults, test coverage, flip-flop, clock pulse,
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Construction of BILBO FF with Soft-Error-Tolerant Capability Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/05/01 Vol. E94-D No. 5 pp. 1045-1050 Type of Manuscript: PAPER Category: Dependable Computing Keyword: soft-error-tolerance, DFT (design for test), BISER (built-in soft-error resilience), BILBO (built-in logic block observer), reconfigurable C-element,
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Single-Event-Upset Tolerant RS Flip-Flop with Small Area Kazuteru NAMBA Kengo NAKASHIMA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/12/01 Vol. E93-D No. 12 pp. 3407-3409 Type of Manuscript: LETTER Category: Dependable Computing Keyword: soft error, single-event-upset (SEU) tolerance, reset-set flip-flop (RS-FF), interlocking feedback loop,
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Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 pp. 2295-2303 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: two-rail logic circuit, path delay fault, testability, functional sensitizability, over-testing,
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Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability Shuangyu RUAN Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/08/01 Vol. E92-D No. 8 pp. 1534-1541 Type of Manuscript: PAPER Category: Dependable Computing Keyword: soft error, wide pulse, flip-flop, C-element, delay element,
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Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths Kentaroh KATOH Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/03/01 Vol. E92-D No. 3 pp. 433-442 Type of Manuscript: PAPER Category: Dependable Computing Keyword: dual circuits, master and slave scan paths, delay fault testing, concurrent error detection, DFT,
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Design for Delay Fault Testability of 2-Rail Logic Circuits Kentaroh KATOH Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/02/01 Vol. E92-D No. 2 pp. 336-341 Type of Manuscript: LETTER Category: Dependable Computing Keyword: 2-rail logic circuits, design for testability, delay fault testing, scan design, set-reset operation,
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Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/02/01 Vol. E92-D No. 2 pp. 269-282 Type of Manuscript: PAPER Category: Dependable Computing Keyword: test compression, statistical coding, run-length coding, delay fault testing, two-pattern testing, scan testing,
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Redundant Design for Wallace Multiplier Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/09/01 Vol. E89-D No. 9 pp. 2512-2524 Type of Manuscript: PAPER Category: Dependable Computing Keyword: Wallace multiplier, bit-slice reconfiguration redundant design, defect-tolerance, yield,
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Proposal of Testable Multi-Context FPGA Architecture Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/05/01 Vol. E89-D No. 5 pp. 1687-1693 Type of Manuscript: PAPER Category: Dependable Computing Keyword: multi-context FPGA, single stuck-at fault, design for testability,
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Scan Design for Two-Pattern Test without Extra Latches Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/12/01 Vol. E88-D No. 12 pp. 2777-2785 Type of Manuscript: PAPER Category: Dependable Computing Keyword: two-pattern testing, delay fault testing, scan design, enhanced scan,
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Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/09/01 Vol. E88-D No. 9 pp. 2135-2142 Type of Manuscript: PAPER Category: Dependable Computing Keyword: two-pattern testing, adjacency test, deterministic test generation, BIST,
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Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities Kazuteru NAMBA Eiji FUJIWARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/06/01 Vol. E85-A No. 6 pp. 1426-1430 Type of Manuscript: LETTER Category: Coding Theory Keyword: unequal error protection code, two-level UEP codes, burst error correcting Fire code,
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