Kazuo KAWAKUBO


Formal Verification of Totally Self-Checking Properties of Combinational Circuits
Kazuo KAWAKUBO Koji TANAKA Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1  pp. 57-62
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Verification
Keyword: 
formal verificationtotally self-checkingfault tolerancebinary decision diagram
 Summary | Full Text:PDF(508.2KB)

An Application of Regular Temporal Logic to Verification of Fail-Safeness of a Comparator for Redundant System
Kazuo KAWAKUBO Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 763-770
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
fail-safefault toleranceformal verificationtemporal logic
 Summary | Full Text:PDF(717.1KB)