Kazunori SHIMIZU


A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems
Qin LIU Seiichiro HIRATSUKA Kazunori SHIMIZU Shinsuke USHIKI Satoshi GOTO Takeshi IKENAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 449-456
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
video surveillance systemmotion estimationME-MC processorquadtreelow power consumption
 Summary | Full Text:PDF(1MB)

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
Kazunori SHIMIZU Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1054-1061
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low-density parity-check codemessage-passing algorithmintermediate message compression techniqueclock gated shift register for intermediate message
 Summary | Full Text:PDF(451.3KB)

Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms
Qi WANG Kazunori SHIMIZU Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1964-1971
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Architecture for Communication/Server Systems
Keyword: 
area and power efficient fully-parallel LDPC decoderimproved simplified min-sum algorithmspower-saved strategy
 Summary | Full Text:PDF(514.3KB)

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule
Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3602-3612
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low-density parity-check codesparallel LDPC decoder architecturemessage-passing algorithmFIFO-based buffering
 Summary | Full Text:PDF(1017.1KB)

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule
Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 969-978
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low-density parity-check codespartially-parallel LDPC decodermessage-passing algorithmFPGA
 Summary | Full Text:PDF(748.2KB)

Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving
Kazunori SHIMIZU Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1526-1537
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Adaptive Signal Processing
Keyword: 
dynamic reconfigurable systemadaptive FECReed-Solomon code with interleaving
 Summary | Full Text:PDF(705.6KB)

FPGA-Based Reconfigurable Adaptive FEC
Kazunori SHIMIZU Jumpei UCHIDA Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3036-3046
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
dynamic reconfigurable systemadaptive FECFPGAReed Solomon codes
 Summary | Full Text:PDF(493.8KB)