Kazumasa YANAGISAWA


Investigations of Optimum Tier Architectures for ASICs
Kan TAKEUCHI Kazumasa YANAGISAWA Kazuko SAKAMOTO Teruya TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/11/01
Vol. E87-A  No. 11  pp. 2983-2989
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
packing efficiencyinterconnectRent's ruleASICs
 Summary | Full Text:PDF(1.4MB)

µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP
Yusuke KANNO Hiroyuki MIZUNO Nobuhiro OODAIRA Yoshihiko YASU Kazumasa YANAGISAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 589-597
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
low-costSystem-on-ChipSoCSystem-in-PackageSiPhierarchical I/O designsignal-level convertersignal wall functionlow-powerinterconnect circuit
 Summary | Full Text:PDF(967.2KB)

Efficient Application of Hot-Carrier Reliability Simulation to Delay Library Screening for Reliability of Logic Designs
Hisako SATO Mariko OHTSUKA Kazuya MAKABE Yuichi KONDO Kazumasa YANAGISAWA Peter M. LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/05/01
Vol. E86-C  No. 5  pp. 842-849
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
hot-carriercircuit reliabilitysimulationdelay librarylogic design
 Summary | Full Text:PDF(1.1MB)

CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip
Shoji SHUKURI Kazumasa YANAGISAWA Koichiro ISHIBASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6  pp. 734-739
Type of Manuscript:  Special Section PAPER (Special Issue on Nonvolatile Memories)
Category: Flash Memories
Keyword: 
ie-FlashEPROMfuse and redundancy
 Summary | Full Text:PDF(1005.6KB)

Low-Power and High-Speed Advantages of DRAM-Logic Integration for Multimedia Systems
Takao WATANABE Ryo FUJITA Kazumasa YANAGISAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12  pp. 1523-1531
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
DRAM-integrated chipembedded DRAMcomputer graphicsmain memory
 Summary | Full Text:PDF(703.7KB)