Kazuki INOUE


Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core
Motoki AMAGASAKI Yuki NISHITANI Kazuki INOUE Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI 
Publication:   
Publication Date: 2017/04/01
Vol. E100-D  No. 4  pp. 633-644
Type of Manuscript:  INVITED PAPER (Special Section on Award-winning Papers)
Category: 
Keyword: 
fault tolerantfault recoveryFPGA-IP
 Summary | Full Text:PDF(2.6MB)

FPGA Design Framework Combined with Commercial VLSI CAD
Qian ZHAO Kazuki INOUE Motoki AMAGASAKI Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1602-1612
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
FPGACADrouting
 Summary | Full Text:PDF(1.2MB)

An Easily Testable Routing Architecture and Prototype Chip
Kazuki INOUE Masahiro KOGA Motoki AMAGASAKI Masahiro IIDA Yoshinobu ICHIDA Mitsuro SAJI Jun IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 303-313
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
design for testabilityhomogeneous architecturetest methodprototype chip
 Summary | Full Text:PDF(3.3MB)

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
Masahiro IIDA Masahiro KOGA Kazuki INOUE Motoki AMAGASAKI Yoshinobu ICHIDA Mitsuro SAJI Jun IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 548-556
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
reconfigurable logicFeRAMpower-gatingnon-volatile flip-flopNV-FFVGLC
 Summary | Full Text:PDF(5.2MB)