Kazuhiro NAKAMURA


Integration of Spectral Feature Extraction and Modeling for HMM-Based Speech Synthesis
Kazuhiro NAKAMURA Kei HASHIMOTO Yoshihiko NANKAKU Keiichi TOKUDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/06/01
Vol. E97-D  No. 6  pp. 1438-1448
Type of Manuscript:  Special Section PAPER (Special Section on Advances in Modeling for Real-world Speech Information Processing and its Application)
Category: HMM-based Speech Synthesis
Keyword: 
integrative modelHMM-based speech synthesisacoustic modelingmel-cepstral analysistrajectory HMM
 Summary | Full Text:PDF(1.7MB)

A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition
Kazuhiro NAKAMURA Ryo SHIMAZAKI Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 456-467
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
speech recognitionhidden Markov model (HMM)VLSI architectureisolated word recognition
 Summary | Full Text:PDF(2.3MB)

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing
Kazuhiro NAKAMURA Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/02/01
Vol. E93-D  No. 2  pp. 300-305
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
speech recognitionhidden Markov model (HMM)VLSI architecture
 Summary | Full Text:PDF(549KB)

Multi-Cycle Path Detection Based on Propositional Satisfiability with CNF Simplification Using Adaptive Variable Insertion
Kazuhiro NAKAMURA Shinji MARUOKA Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2600-2607
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
timing verificationmaximum delay analysismulti-cycle pathspropositional satisfiability
 Summary | Full Text:PDF(365KB)

Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
Kazuhiro NAKAMURA Shinji KIMURA Kazuyoshi TAKAGI Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2515-2520
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
Keyword: 
timing verificationmaximum delay analysismultiple clock operationfalse path
 Summary | Full Text:PDF(546.5KB)