Kazuaki MURAKAMI


A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits
Hiroshi KATAOKA Hiroaki HONDA Farhad MEHDIPOUR Nobuyuki YOSHIKAWA Akira FUJIMAKI Hiroyuki AKAIKE Naofumi TAKAGI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 141-148
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
single flux quantumreconfigurable data-pathaccelerator
 Summary | Full Text:PDF(2MB)

Optimisations Techniques for the Automatic ISA Customisation Algorithm
Antoine TROUVE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 437-440
Type of Manuscript:  Special Section LETTER (Special Section on Reconfigurable Systems)
Category: Design Optimisation
Keyword: 
reconfigurable computingcustom instruction generationoptimisation
 Summary | Full Text:PDF(164.7KB) | (Errata[Uploaded on February 1,2012])

NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers
Hideki MIWA Ryutaro SUSUKITA Hidetomo SHIBAMURA Tomoya HIRAO Jun MAKI Makoto YOSHIDA Takayuki KANDO Yuichiro AJIMA Ikuo MIYOSHI Toshiyuki SHIMIZU Yuji OINAGA Hisashige ANDO Yuichi INADOMI Koji INOUE Mutsumi AOYAGI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/12/01
Vol. E94-D  No. 12  pp. 2298-2308
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
discrete event simulationmultiprocessor interconnectionparallel processing
 Summary | Full Text:PDF(1.5MB)

Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
Farhad MEHDIPOUR Hamid NOORI Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3182-3192
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
reconfigurable instruction-set processoranalytical modelingdesign space explorationdata flow graph accelerator
 Summary | Full Text:PDF(1009.8KB)

Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode
Pradeep RAO Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/10/01
Vol. E92-C  No. 10  pp. 1265-1275
Type of Manuscript:  Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors)
Category: 
Keyword: 
processor microarchitectureJava virtual machineperformance bottlenecksempirical models
 Summary | Full Text:PDF(213.1KB)

Reducing On-Chip DRAM Energy via Data Transfer Size Optimization
Takatsugu ONO Koji INOUE Kazuaki MURAKAMI Kenji YOSHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 433-443
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
low powervariable line-sizeon-chip DRAMhigh bandwidthembedded systems
 Summary | Full Text:PDF(497.8KB)

Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems
Makoto SUGIHARA Yusuke MATSUNAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3451-3460
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
maskless lithographymulti-column-cellscharacter projectionvariable-shaped beamthroughput
 Summary | Full Text:PDF(754.9KB)

Performance Models for MPI Collective Communications with Network Contention
Hyacinthe NZIGOU MAMADOU Takeshi NANRI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/04/01
Vol. E91-B  No. 4  pp. 1015-1024
Type of Manuscript:  PAPER
Category: Network
Keyword: 
MPIcollective communicationsperformance predictionqueuing theorycontention issue
 Summary | Full Text:PDF(518.5KB)

Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems
Hamid NOORI Maziar GOUDARZI Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 418-431
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
temperature-aware designcache memoryleakage currentlow energyembedded systems
 Summary | Full Text:PDF(1.7MB)

A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions
Hamid NOORI Farhad MEHDIPOUR Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 497-508
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
custom instructionsextensible processorreconfigurable functional unitconditional execution
 Summary | Full Text:PDF(1.5MB)

Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems
Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 410-417
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
single event upsetSRAMDRAMreliabilitycache architecturetask scheduling
 Summary | Full Text:PDF(558.2KB)

Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits
Naofumi TAKAGI Kazuaki MURAKAMI Akira FUJIMAKI Nobuyuki YOSHIKAWA Koji INOUE Hiroaki HONDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/03/01
Vol. E91-C  No. 3  pp. 350-355
Type of Manuscript:  INVITED PAPER (Special Section on Recent Progress in Superconductive Digital Electronics)
Category: 
Keyword: 
superconductorrapid single-flux-quantum circuitreconfigurable data-pathhigh-performance computingsupercomputer
 Summary | Full Text:PDF(297.2KB)

Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs
Farhad MEHDIPOUR Hamid NOORI Morteza SAHEB ZAMANI Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12  pp. 1956-1966
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable Device and Design Tools
Keyword: 
reconfigurable acceleratorconditional executioncontrol data flow graphtemporal partitioningreconfigurable processor
 Summary | Full Text:PDF(1.5MB)

Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems
Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1983-1991
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Design Technology
Keyword: 
soft errorreliabilityestimationcomputer systemsinstruction-set simulation
 Summary | Full Text:PDF(670.7KB)

A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips
Mariko SAKAMOTO Akira KATSUNO Go SUGIZAKI Toshio YOSHIDA Aiichiro INOUE Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1972-1982
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Architecture for Communication/Server Systems
Keyword: 
enterprise server systemcache coherencedistributed shared memoryonline transaction processingperformance evaluation
 Summary | Full Text:PDF(4.9MB)

Technology Mapping Technique for Increasing Throughput of Character Projection Lithography
Makoto SUGIHARA Kenta NAKAMURA Yusuke MATSUNAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 1012-1020
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Lithography-Related Techniques
Keyword: 
maskless lithographycharacter projectionvariable-shaped beamtechnology mappingthroughput
 Summary | Full Text:PDF(715.6KB)

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment
Makoto SUGIHARA Taiga TAKATA Kenta NAKAMURA Ryoichi INANAMI Hiroaki HAYASHI Katsumi KISHIMOTO Tetsuya HASEBE Yukihiro KAWANO Yusuke MATSUNAGA Kazuaki MURAKAMI Katsuya OKUMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 377-383
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: CAD
Keyword: 
cell librarycharacter projectionelectron beamEB shotsthroughputoptimizationinteger linear programming
 Summary | Full Text:PDF(427.7KB)

Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 862-868
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low powercacheleakage
 Summary | Full Text:PDF(1014.7KB)

Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints
Makoto SUGIHARA Kazuaki MURAKAMI Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3174-3184
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
core-based designSOCTAMtest architecturefloorplantest scheduling
 Summary | Full Text:PDF(332.4KB)

Evaluating Online Hot Instruction Sequence Profilers for Dynamically Reconfigurable Functional Units
Takanori HAYASHIDA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5  pp. 901-909
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
online profilingdynamically reconfigurable computinghardware profiling
 Summary | Full Text:PDF(423.7KB)

Relaxing Constraints due to Data and Control Dependences
Katsuhiko METSUGI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5  pp. 920-928
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
TLSPILPdata dependencecontrol dependencevalue prediction
 Summary | Full Text:PDF(391.1KB)

Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4  pp. 799-805
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low powerinstruction ROMembedded systemsencoding
 Summary | Full Text:PDF(710.3KB)

Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 279-287
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
cachelow powerlook uprun time
 Summary | Full Text:PDF(726.5KB)

Trends in High-Performance, Low-Power Cache Memory Architectures
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 304-314
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
cachelow powerhigh performancemicroprocessorsurvey
 Summary | Full Text:PDF(238.5KB)

Trends in High-Performance, Low-Power Processor Architectures
Kazuaki MURAKAMI Hidetaka MAGOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 131-138
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
processor architecturehigh performance designlow power design
 Summary | Full Text:PDF(185.1KB)

A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11  pp. 1716-1723
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
cachelow powervariable line-sizemerged DRAM/logic LSIshigh bandwidth
 Summary | Full Text:PDF(1001.2KB)

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Vol. E83-D  No. 5  pp. 1048-1057
Type of Manuscript:  PAPER
Category: Computer System Element
Keyword: 
cachevariable line-sizemerged DRAM/logic LSIshigh bandwidth
 Summary | Full Text:PDF(1015.7KB)

A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection
Koji INOUE Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 186-194
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
cachelow powerlow energyway predictionhigh performance
 Summary | Full Text:PDF(1015.4KB)

FOREWORD
Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1373-1373
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(88.5KB)

Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs
Taku OHSAWA Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1455-1462
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
DRAMDRAM refreshmerged DRAM/logicsystem LSIlow power
 Summary | Full Text:PDF(737.9KB)

Analyzing and Reducing the Impact of Shorter Data Retention Time on the Performance of Merged DRAM/Logic LSIs
Koji KAI Akihiko INOUE Taku OHSAWA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1448-1454
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
merged DRAM/logic LSIsdata retention timerefreshyield
 Summary | Full Text:PDF(664.2KB)

High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1438-1447
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
cachemerged DRAM/logic LSIsmemory system
 Summary | Full Text:PDF(938.1KB)

Tradeoffs in Processor Design for Superscalar Architectures
Kazuaki MURAKAMI Morihiro KUGA Oubong GWUN Shinji TOMITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1991/11/25
Vol. E74-D  No. 11  pp. 3883-3893
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
 Summary | Full Text:PDF(905.4KB)