Katsushige MATSUBARA


A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems
Seiji MOCHIZUKI Katsushige MATSUBARA Keisuke MATSUMOTO Chi Lan Phuong NGUYEN Tetsuya SHIBAYAMA Kenichi IWATA Katsuya MIZUMOTO Takahiro IRITA Hirotaka HARA Toshihiro HATTORI 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2878-2887
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
video processingautomotivelow latencymemory-access-data compression
 Summary | Full Text:PDF(4.3MB)

2-D Pipelined Adaptive Filters Based on 2-D Delayed LMS Algorithm
Katsushige MATSUBARA Kiyoshi NISHIKAWA Hitoshi KIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6  pp. 1009-1014
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
pipeliningtwo-dimensional LMS algorithmdelayed LMS algorithm
 Summary | Full Text:PDF(416.8KB)