Katsumi DOSAKA


A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications
Katsumi DOSAKA Daisuke OGAWA Takahito KUSUMOTO Masayuki MIYAMA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 685-695
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
TCAMcharge recyclinglow powerlow noiselow operating current
 Summary | Full Text:PDF(4.3MB)

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform
Hiroki SHIMANO Fukashi MORISHITA Katsumi DOSAKA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/03/01
Vol. E92-C  No. 3  pp. 356-363
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
power managementlow voltage scalabilitySoC memory platform
 Summary | Full Text:PDF(1.2MB)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Takayuki GYOHTEN Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1409-1418
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
content addressable memoryCAMmatrix-processing architectureSIMDbit-serial and word-paralleltable-lookup codingDCTHuffman codingJPEG
 Summary | Full Text:PDF(624KB)

A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform
Hiroki SHIMANO Fukashi MORISHITA Katsumi DOSAKA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1927-1935
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Next-Generation Memory for SoC
Keyword: 
DFM RAM2 cell/bitlow voltage scalabilityscreening testSoC memory platform
 Summary | Full Text:PDF(1.2MB)

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor
Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/08/01
Vol. E90-D  No. 8  pp. 1312-1315
Type of Manuscript:  LETTER
Category: Image Processing and Video Processing
Keyword: 
DCTfast DCTmatrix-processing engineSIMDbit-serial and word-parallel
 Summary | Full Text:PDF(485KB)

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
Fukashi MORISHITA Hideyuki NODA Isamu HAYASHI Takayuki GYOHTEN Mako OKAMOTO Takashi IPPOSHI Shigeto MAEGAWA Katsumi DOSAKA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 765-771
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
SOIcapacitorlessDRAMlow powerdata retention
 Summary | Full Text:PDF(932.3KB)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer
Takeshi KUMAKI Yasuto KURODA Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 334-345
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
content addressable memoryCAMHuffman codingparallel processingpipelinecode word table
 Summary | Full Text:PDF(2.1MB)

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC
Hideyuki NODA Katsumi DOSAKA Hans Jurgen MATTAUSCH Tetsushi KOIDE Fukashi MORISHITA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1612-1619
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
soft errorECCTCAMembeddedDRAM
 Summary | Full Text:PDF(1.2MB)

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design
Takayuki GYOHTEN Fukashi MORISHITA Isamu HAYASHI Mako OKAMOTO Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1519-1525
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
PVT variationtemperature detectionseries regulator
 Summary | Full Text:PDF(1.5MB)

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros
Akira YAMAZAKI Fukashi MORISHITA Naoya WATANABE Teruhiko AMANO Masaru HARAGUCHI Hideyuki NODA Atsushi HACHISUKA Katsumi DOSAKA Kazutami ARIMOTO Setsuo WAKE Hideyuki OZAKI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/10/01
Vol. E88-C  No. 10  pp. 2020-2027
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
embedded memoryDRAMvoltage marginlow voltagesystem on chip
 Summary | Full Text:PDF(908.3KB)

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh
Hideyuki NODA Kazunari INOUE Hans Jurgen MATTAUSCH Tetsushi KOIDE Katsumi DOSAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Kenji ANAMI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 622-629
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
CMOSTernary CAMnetworkrefresh
 Summary | Full Text:PDF(1.3MB)

An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester
Naoya WATANABE Fukashi MORISHITA Yasuhiko TAITO Akira YAMAZAKI Tetsushi TANIZAKI Katsumi DOSAKA Yoshikazu MOROOKA Futoshi IGAUE Katsuya FURUE Yoshihiro NAGURA Tatsunori KOMOIKE Toshinori MORIHARA Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 624-634
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
embedded DRAMvarious DRAM macroslow voltage operationshort TATBIST
 Summary | Full Text:PDF(5.2MB)

Accomplishment of At-Speed BISR for Embedded DRAMs
Yoshihiro NAGURA Yoshinori FUJIWARA Katsuya FURUE Ryuji OHMURA Tatsunori KOMOIKE Takenori OKITAKA Tetsushi TANIZAKI Katsumi DOSAKA Kazutami ARIMOTO Yukiyoshi KODA Tetsuo TADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1498-1505
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: BIST
Keyword: 
at-speed testBISRembedded DRAMtest cost reduction
 Summary | Full Text:PDF(2.2MB)

A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
Akira YAMAZAKI Takeshi FUJINO Kazunari INOUE Isamu HAYASHI Hideyuki NODA Naoya WATANABE Fukashi MORISHITA Katsumi DOSAKA Yoshikazu MOROOKA Shinya SOEDA Kazutami ARIMOTO Setsuo WAKE Kazuyasu FUJISHIMA Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/09/01
Vol. E85-C  No. 9  pp. 1697-1708
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
embedded DRAMsystem on chip3-D graphics concurrent operation
 Summary | Full Text:PDF(2.2MB)

A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU
Katsumi DOSAKA Akira YAMAZAKI Naoya WATANABE Hideaki ABE Jun OHTANI Toshiyuki OGAWA Kazunori ISHIHARA Masaki KUMANOYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C  No. 7  pp. 948-956
Type of Manuscript:  Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory
Keyword: 
 Summary | Full Text:PDF(752.8KB)

Trends in High-Speed DRAM Architectures
Masaki KUMANOYA Toshiyuki OGAWA Yasuhiro KONISHI Katsumi DOSAKA Kazuhiro SHIMOTORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4  pp. 472-481
Type of Manuscript:  INVITED PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
reviewDRAMhigh-speed DRAMmain memorygraphics memoryperformance gapbandwidth bottleneckperformance comparisonhigh-speed I/O interfaceunified memorysystem integration
 Summary | Full Text:PDF(851.6KB)