IEICE SEARCH SYSTEM

Katsuhisa YAMANAKA

Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units Md Belayet ALI Takashi HIRAYAMA Katsuhisa YAMANAKA Yasuaki NISHITANI
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2231-2243 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: reversible function, reversible adder/subtractor, reversible arithmetic logic unit, incompletely-specified function, operation assignment, quantum cost, multiple-control Toffoli,
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Enumerating Floorplans with Columns Katsuhisa YAMANAKA Md. Saidur RAHMAN Shin-ichi NAKANO
Publication: Publication Date: 2018/09/01 Vol. E101-A No. 9 pp. 1392-1397 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: enumeration, floorplan, algorithm,
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Enumeration, Counting, and Random Generation of Ladder Lotteries Katsuhisa YAMANAKA Shin-ichi NAKANO
Publication: Publication Date: 2017/03/01 Vol. E100-D No. 3 pp. 444-451 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science — New Trends in Theoretical Computer Science —) Category: Keyword: enumeration, counting, random generation, ladder lottery,
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Uniformly Random Generation of Floorplans Katsuhisa YAMANAKA Shin-ichi NAKANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/03/01 Vol. E99-D No. 3 pp. 624-629 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science---Developments of the Theory of Algorithms and Computation---) Category: Keyword: random generation, algorithm, floorplan, mosaic floorplan, classification tree,
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Another Optimal Binary Representation of Mosaic Floorplans Katsuhisa YAMANAKA Shin-ichi NAKANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/06/01 Vol. E98-A No. 6 pp. 1223-1224 Type of Manuscript: Special Section LETTER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: algorithm, coding, decoding, floorplan, mosaic floorplan,
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A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits Takashi HIRAYAMA Hayato SUGAWARA Katsuhisa YAMANAKA Yasuaki NISHITANI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/09/01 Vol. E97-D No. 9 pp. 2253-2261 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Reversible/Quantum Computing Keyword: reversible logic circuits, Toffoli gates, lower bound, logic minimization,
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Efficient Enumeration of All Ladder Lotteries with k Bars Katsuhisa YAMANAKA Shin-ichi NAKANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/06/01 Vol. E97-A No. 6 pp. 1163-1170 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: algorithm, enumeration, ladder lottery, family tree,
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A Compact Encoding of Rectangular Drawings with Edge Lengths Shin-ichi NAKANO Katsuhisa YAMANAKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 pp. 1032-1035 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: graph, algorithm, encoding, rectangular drawing, grid rectangular drawing,
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Enumerating All Rooted Trees Including k Leaves Masanobu ISHIKAWA Katsuhisa YAMANAKA Yota OTACHI Shin-ichi NAKANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/03/01 Vol. E95-D No. 3 pp. 763-768 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science – Mathematical Foundations and Applications of Computer Science and Algorithms –) Category: Keyword: graph algorithm, enumeration, rooted tree, family tree,
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Random Generation and Enumeration of Proper Interval Graphs Toshiki SAITOH Katsuhisa YAMANAKA Masashi KIYOMI Ryuhei UEHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/07/01 Vol. E93-D No. 7 pp. 1816-1823 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: counting, enumeration, proper interval graphs, random generation, unit interval graphs,
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Computational Complexities of University Interview Timetabling Naoyuki KAMIYAMA Yuuki KIYONARI Eiji MIYANO Shuichi MIYAZAKI Katsuhisa YAMANAKA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/02/01 Vol. E92-D No. 2 pp. 130-140 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science) Category: Keyword: timetable, scheduling, optimization, computational complexity,
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A Compact Encoding of Rectangular Drawings with Efficient Query Supports Katsuhisa YAMANAKA Shin-ichi NAKANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/09/01 Vol. E91-A No. 9 pp. 2284-2291 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: graph, algorithm, graph encoding, rectangular drawing, query supports,
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Constant Time Generation of Integer Partitions Katsuhisa YAMANAKA Shin-ichiro KAWANO Yosuke KIKUCHI Shin-ichi NAKANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/05/01 Vol. E90-A No. 5 pp. 888-895 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: algorithm, generation, integer partition, the family tree,
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Constant Time Generation of Rectangular Drawings with Exactly n Faces Satoshi YOSHII Daisuke CHIGIRA Katsuhisa YAMANAKA Shin-ichi NAKANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/09/01 Vol. E89-A No. 9 pp. 2445-2450 Type of Manuscript: LETTER Category: Algorithms and Data Structures Keyword: graphs, rectangular drawings, enumeration,
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Coding Floorplans with Fewer Bits Katsuhisa YAMANAKA Shin-ichi NAKANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/05/01 Vol. E89-A No. 5 pp. 1181-1185 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: graphs, algorithms,
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