Junichi MIYAKOSHI


A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core
Osamu NISHII Yoichi YUYAMA Masayuki ITO Yoshikazu KIYOSHIGE Yusuke NITTA Makoto ISHIKAWA Tetsuya YAMADA Junichi MIYAKOSHI Yasutaka WADA Keiji KIMURA Hironori KASAHARA Hideo MAEJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 663-669
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
heterogeneousinstruction setMMU
 Summary | Full Text:PDF(2.7MB)

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
Yuichiro MURACHI Junichi MIYAKOSHI Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Fang YIN Jangchung LEE Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 465-478
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
low powermotion estimationH.264systolic arrayMBAFFSRAM
 Summary | Full Text:PDF(1.8MB)

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
Yuichiro MURACHI Yuki FUKUYAMA Ryo YAMAMOTO Junichi MIYAKOSHI Hiroshi KAWAGUCHI Hajime ISHIHARA Masayuki MIYAMA Yoshio MATSUDA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 457-464
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
optical flowreal-time video recognitionVLSI processor
 Summary | Full Text:PDF(1.2MB)

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture
Junichi MIYAKOSHI Yuichiro MURACHI Tetsuro MATSUNO Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3623-3633
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low powermotion estimationH.264SIMDsystolic array
 Summary | Full Text:PDF(1.9MB)

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond
Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Kentaro KAWAKAMI Junichi MIYAKOSHI Shinji MIKAMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3634-3641
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
SRAMDVSVth-variation-tolerantlow power
 Summary | Full Text:PDF(1.2MB)

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing
Junichi MIYAKOSHI Yuichiro MURACHI Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1629-1636
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
SRAMlow powerparallel processingimage signal processingH.264MPEG
 Summary | Full Text:PDF(1.7MB)

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation
Noriyuki MINEGISHI Junichi MIYAKOSHI Yuki KURODA Tadayoshi KATAGIRI Yuki FUKUYAMA Ryo YAMAMOTO Masayuki MIYAMA Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 230-242
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: System LSIs and Microprocessors
Keyword: 
optical flowprocessor architecturevideo segmentation
 Summary | Full Text:PDF(4.2MB)

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application
Yuichiro MURACHI Koji HAMANO Tetsuro MATSUNO Junichi MIYAKOSHI Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3492-3499
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low powermotion estimationMPEG2HDTVIP
 Summary | Full Text:PDF(1.7MB)

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation
Junichi MIYAKOSHI Yuichiro MURACHI Koji HAMANO Tetsuro MATSUNO Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 559-569
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
motion estimationMPEGH.264block-matching
 Summary | Full Text:PDF(719.6KB)

VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding
Masayuki MIYAMA Junichi MIYAKOSHI Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 466-474
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
MPEGmotion estimationgradient based methodsteepest descent methodlow powerVLSI
 Summary | Full Text:PDF(731.6KB)

An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video
Masayuki MIYAMA Osamu TOOYAMA Naoki TAKAMATSU Tsuyoshi KODAKE Kazuo NAKAMURA Ai KATO Junichi MIYAKOSHI Kousuke IMAMURA Hideo HASHIMOTO Satoshi KOMATSU Mikio YAGI Masao MORIMOTO Kazuo TAKI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 561-569
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword: 
HDTVMPEGmotion estimation processorGradient Descent Search algorithmSIMD datapath architecture
 Summary | Full Text:PDF(1.1MB)