Jun Kyoung KIM

A Plan-Generation-Evaluation Framework for Design Space Exploration of Digital Systems Design
Jun Kyoung KIM  Tag Gon KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/03/01
Vol. E89-A  No. 3  pp. 772-781
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
design space exploration,  plan-generation-evaluation framework,  graph pruning,  attributed AND-OR graph, 
  Summary |  Full Text:PDF (1.9MB)
Top-Down Retargetable Framework with Token-Level Design for Accelerating Simulation Speed of Processor Architecture
Jun Kyoung KIM  Ho Young KIM  Tag Gon KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3089-3098
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation Accelerator
Keyword: 
retargetable simulator,  trace-driven simulation,  token-level simulation, 
  Summary |  Full Text:PDF (1.3MB)