Jun FURUTA


A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process
Haruki MARUOKA Masashi HIFUMI Jun FURUTA Kazutoshi KOBAYASHI 
Publication:   
Publication Date: 2018/04/01
Vol. E101-C  No. 4  pp. 273-280
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
single event effectsoft errorα particleneutronheavy ionFDSOIflip-floplow-power consumption
 Summary | Full Text:PDF(1.4MB)

Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model
Takuya KOMAWAKI Michitarou YABUUCHI Ryo KISHIDA Jun FURUTA Takashi MATSUMOTO Kazutoshi KOBAYASHI 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2758-2763
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Random Telegraph NoisereliabilityVerilog-AMS
 Summary | Full Text:PDF(2.1MB)

Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets
Jun FURUTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C  No. 4  pp. 298-303
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
Neutron-induced Soft ErrorMultiple Cell Upset (MCU)cell distancewell-contact densityFlip-Flop
 Summary | Full Text:PDF(796.1KB)

A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect
Kuiyuan ZHANG Jun FURUTA Ryosuke YAMAMOTO Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 511-517
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
DMRsoft errorMCUdevice simulation
 Summary | Full Text:PDF(2MB)

Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures
Chikara HAMANAKA Ryosuke YAMAMOTO Jun FURUTA Kanto KUBOTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2669-2675
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
soft errorhardened designvariabilitytest structureshift register
 Summary | Full Text:PDF(3.1MB)

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
Jun FURUTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 340-346
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
TMRbuilt-in soft errorSEUSET
 Summary | Full Text:PDF(385.2KB)