Jing-Yang JOU

Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
Juinn-Dar HUANG  Chia-I CHEN  Wan-Ling HSU  Yen-Ting LIN  Jing-Yang JOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/02/01
Vol. E95-A  No. 2  pp. 559-566
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Behavioral synthesis,  distributed register-file,  performance optimization,  low-power,  resource binding,  scheduling, 
  Summary |  Full Text:PDF
Efficient Vector Compaction Methods for Power Estimation with Consecutive Sampling Techniques
Chih-Yang HSU  Chien-Nan Jimmy LIU  Jing-Yang JOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/11/01
Vol. E87-A  No. 11  pp. 2973-2982
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
power estimation,  vector compaction,  grouping,  consecutive sampling,  random sampling, 
  Summary |  Full Text:PDF
An Efficient Power Model for IP-Level Complex Designs
Chih-Yang HSU  Chien-Nan Jimmy LIU  Jing-Yang JOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/08/01
Vol. E86-A  No. 8  pp. 2073-2080
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
IP-level,  power model,  lookup table,  dynamic grouping, 
  Summary |  Full Text:PDF
Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs
Hsien-Ho CHUANG  Jing-Yang JOU  C. Bernard SHUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/20
Vol. E83-A  No. 12  pp. 2545-2551
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Optimization
Keyword: 
technology mapping,  FPGA,  hard-wired,  non-homogeneous,  XC4000, 
  Summary |  Full Text:PDF
A New Method for Constructing IP Level Power Model Based on Power Sensitivity
Heng-Liang HUANG  Jiing-Yuan LIN  Wen-Zen SHEN  Jing-Yang JOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/20
Vol. E83-A  No. 12  pp. 2431-2438
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Methodology
Keyword: 
IP,  power model,  power sensitivity, 
  Summary |  Full Text:PDF
Internet-Based Hierarchical Floorplan Design
Jiann-Horng LIN  Jing-Yang JOU  Iris Hui-Ru JIANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/20
Vol. E82-A  No. 11  pp. 2414-2423
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
internet,  floorplanning, 
  Summary |  Full Text:PDF
A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping
Jie-Hong JIANG  Jing-Yang JOU  Juinn-Dar HUANG  Jung-Shian WEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/20
Vol. E80-A  No. 10  pp. 1813-1819
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagrams,  equivalent class,  Roth-Karp decomposition,  LUT-based FPGA, 
  Summary |  Full Text:PDF